DDR3 speed, Altera vs Xilinx

Austin,

Thanks for your reply. I know this is kinda flamebait for you and your competitor, and I will review all postings with care.

I have put my xilinx dealer to the work of finding real solution (not powerpoints, or postings on this site ;)) working at high speed. I don't really think we will get to 533Mhz, but want to compare REAL performance. For our upcoming design DDR speed and IO count is the main criterias for selection.

A 32bit design is of no help for me. Altera claims to have 12 dedicated DQS pins on every side, where 2 sides can run at 533Mhz on their fastest device (wich is theoretically 216 pins when using 9bit ECC mem) . They claim to have 72bit real hw proving this, and Im waiting to see how this is done. For Xilinx, I have no idea how wide bus they can do. I've only seen 64bit designs at much lower rate for now. I am hoping they(you?) can show me something better.

I know there is a lot of the "marketing numbers" out there and my colleagues have wide experience on trying to achive "marketing" numbers (and even got the supplier convinced that their numbers didn't work).

Because of this, I need to see a working design before aiming at any number.

Best regards, Morten

Reply to
Morten Leikvoll
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Me too. I need to stream 60 Bits at 833MHz in our next project to a large RAM, so depending on controller overhead something like 64 bit at 500MHz DDR would be a good thing to have.

Kolja Sulimma

Reply to
Kolja Sulimma

Morten,

Like I advised, you need to get your local FAE in to see you. We have demo boards for memory, networking, PCI Express, etc. so it is not hard to see what we actually sell as a "realization" of our claims.

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(memory pcb for V5)
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(PCIe pcb for V5) ...

Can you do better than we do on our own demo pcb's? Yes, you can, but that does require more work.

The memory interface generator (MIG) is designed to "solve" the problems (not create new ones), so it is, by its very nature, conservative. What is more important: specifying your memory and pressing a button and generating a working design, or starting from scratch and squeezing the best performance possible out of the interface? Your choice, we will support you.

Since our solution in V5 is still general (no hardened features for DDR3), the bus width is whatever you wish. I know of customers who use

288 bit wide bus, as that is 4 X 72, and 72 is the width needed to take advantage of the ECC block which can be used with your external memory (for error check and correct).

I won't waste your time talking about Altera. Having their FAE visit you, and show you their solutions, is another necessary part of the work ahead of you.

Then, you decide.

I may be having fun right now due to Altera's 65nm misfortune, but I am a realist, too, and I know they will "be baaack!"

Austin

Reply to
austin

Better for some things, not for everything. I had several designs using PICs for which AVRs would not have been fast enough. (There are faster AVRs now, but there are faster PICs too.)

If one were to pick parts purely on technical merit of the parts, both would win some designs. However, there's also the tradeoff of saving development time by using parts and tools with which one is already experienced.

Reply to
Eric Smith

yes agreed, at the beginning where it was PIC16C84 vs AT90S1200 it was clear win for AVR, but microchip has no so many new chips that they defenetly win designs where AVR do not fit because of lack of functions or speed or other details.

well both PIC and AVRs are no loosing against 32 bit low cost MCUs eh, I am writing just now "My first STM32" book ;) a ARM that cost less 3 usd runs at 72mhz (also from internal osc!) and has USB and 64KByte flash.. why think of 8 bit micros for designs where the 3 usd price is acceptable? sure for sub 1 usd prices 8 bit MCUs are considered.

Antti

Reply to
Antti

Austin,

Thanks for the information. The ML561 board immediately caught my attention as it seem to support

2x72pin dimms in ddr2 at 333Mhz on a VLX50T -2, but the docs refer to xapp850, wich at the moment has a dead link and is nowhere else to find. Maybe you can direct me to that?

This is a documented number I can relate to :) Also I would guess this design looses a bit of speed as it has some empty x16 simms disturbing many of the signals.

I know all the external stuff needed to improve speed, but I have little detailed control of the internals. Some of the internals can be very hard to get to (like IO skew, delays (to ball), ripple and so on). Often we need to know this to tweak max performance. We need to handle the setup/hold times from the datasheet as a sum of all these unknown parameters, and they may not add up.

Thanks again, Morten

Reply to
Morten Leikvoll

Check out the Altera StratixIII for DDR3 speeds. There is a video demo on the front page that shows it up to 1.067Gbps. Not sure if Xilinx can touch that?

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Reply to
pmulliki

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