M Mr.CRC Contact options for registered users Vote on answer posted 12 years ago Thu, May 19, 2011 3:21 AM Show Quoted Text No, only that you can only ever use one clock. ;-) -- _____________________ Mr.CRC Click to see the full signature Reply toMr.CRC Notify me about replies to my post Reply
K KJ Contact options for registered users Vote on answer posted 12 years ago Thu, May 19, 2011 4:54 AM Show Quoted Text Not true. FPGAs implement dual clock FIFOs and memories just fine. Kevin Jennings Reply toKJ Notify me about replies to my post Reply