Counter clocks on both edges sometimes, but not when different IO pin is used

Mr.CRC · 2011-05-14T04:11:09+00:00

Hi:I'm using a Xilinx Spartan 3E FPGA (on the Digilent NEXYS2 500k board)to implement a quadrature encoder simulator, among other things.The qep_sim.v code is shown below. The clock input to qep_sim() ismultiplexed from one of two buffered and isolated external world inputs.The problem is that when the multiplexer selects one clock input, theqep_sim() occasionally counts on a negedge. While, if the other inputis used, it never glitches like this and performs correctly.The 288kHz clocks at the point where they enter the NEXYS2 board havebeen probed and are clean, including when the counting glitch occurs.What is stranger is that if I try to send a copy of the multiplexedclock out to an IO pin to scope it, then the glitching goes away nomatter which clock source is selected.Thanks for ideas on what might be wrong. I suspect it has something todo with non-ideal choices of IO pins for the clock inputs. I didn'thave time to test this today, but I suspect if I simply move theext_sim_clk to a different pin, the problem will go away.I wouldn't be satisfied with this however, as I wish to understand thereal cause of the problem.Here is the multiplexing code (excerpted from a longer module):module shaft ( // Begin QEP related ports // Switch SW0 selects: 0 = ext_sim_clk, 1 = dsp_sim_clk input clk_mux_sel,// Note: signal dsp_sim_clk is being temporarily supplied for// troubleshooting from an identical external buffer circuit// as the ext_sim_clk: input dsp_sim_clk, // sim clk generated by DSP. input ext_sim_clk, // external sim clk input// diagnostic sim clk output. Problem goes away if this is used:// output sim_clk_o, [edited out many lines] ); wire sim_clk; // muxed sim clk to feed to qep_sim.v// Select the simulation clock source: assign sim_clk = clk_mux_sel ? dsp_sim_clk : ext_sim_clk;// Instantiate the QEP simulator. Source for qep_maxcnt is not shown// here for brevity, and since this isn't being used in qs1 at present. qep_sim ...

May 14, 2011 21 Replies

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Mr.CRC 15 years ago

No, only that you can only ever use one clock. ;-)

_____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17

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KJ 15 years ago

Not true. FPGAs implement dual clock FIFOs and memories just fine.

Kevin Jennings

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