Target chip: XCV600e and later XC2V1000 (>1000 units)
This is a very large SOC design that is in its final design and implementation stages. It is basically a video game on a chip. Now we are using distributed ram (64Kb) as asynch ROM memory. With this configuration, the compile time goes up to 30 minutes. Without the ROM, compilation time is a descent 7 minutes.
we tried to remove the rom component, while having before compiled it into an NGC file without IO buffers, thinking that XST will take it as a black box and would eventually run the whole process faster, but the process time dropped by about 4 minutes.
I wanted to know..
1) is there a way of making the compilation faster, without changing computer. 2) is there an actual design methodology that could be applied in order to save time (Im thinking of incremental or modular design)Thanks for any suggestions