Building a MicroBlaze from scratch, unable to run.


I am using a spartan3 development board and trying to learn about MicroBlaze.

My application is simple, I want the bitpattern at the slideswitches to appear on the leds (The board has 8 slideswitches and 8 leds).

If I use the BSB to create my MicroBlaze it works fine. the modules (in Add/Edit cores) the BSB create/use is: microblaze 4.00.a microblaze_0 opb_mdm 2.00.a debug_module lmb_bram_if_cntrl 1.00.b dlmb_cntlr lmb_bram_if_cntrl 1.00.b ilmb_cntlr bram_block 1.00.a lmb_bram opb_gpio 3.01.b LEDs_8Bit opb_gpio 3.01.b DIP_Switches_8Bit dcm_module 1.00.a dcm_0

If I make one from scratch it doesn't work. the module (in Add/Edit cores) I create/use is: lmb_bram_if_cntrl 1.00.b i_bram lmb_bram_if_cntrl 1.00.b d_bram bram_block 1.00.a bram opb_gpio 3.01.b Switch microblaze 4.00.a MyProsessor opb_gpio 3.01.b Leds dcm_module 1.00.a dcm_0

and my c-code is simple (used on both): #include "xparameters.h" #include "xgpio_l.h"

int main() { unsigned char ucData; while(1) { // read from slide switches. ucData = XGpio_mGetDataReg(SWITCH BASEADDR, 1); // put value in LEDs XGpio_mSetDataReg(LEDS BASEADDR, 1, ucData); } return 0; }

The BASEADDR are from the headers xparameters.h in the respective projects.

BSBs ucf file look like this: Net sys_clk_pin LOC=T9; Net sys_rst_pin LOC=l14; ## System level constraints Net sys_clk_pin TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps; Net sys_rst_pin TIG;

## FPGA pin constraints Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=k12; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=p14; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=l12; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=n14; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=p13; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=n12; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=p12; Net fpga_0_LEDs_8Bit_GPIO_d_out_pin LOC=p11; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=k13; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=k14; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=j13; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=j14; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=h13; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=h14; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=g12; Net fpga_0_DIP_Switches_8Bit_GPIO_in_pin LOC=f12;

My ucf file look like this: NET "sys_reset" LOC = "L14" ; NET "sys_clock" LOC = "T9" ; NET "Leds_GPIO_d_out" LOC = "K12" ; NET "Leds_GPIO_d_out" LOC = "P14" ; NET "Leds_GPIO_d_out" LOC = "L12" ; NET "Leds_GPIO_d_out" LOC = "N14" ; NET "Leds_GPIO_d_out" LOC = "P13" ; NET "Leds_GPIO_d_out" LOC = "N12" ; NET "Leds_GPIO_d_out" LOC = "P12" ; NET "Leds_GPIO_d_out" LOC = "P11" ; NET "Switch_GPIO_in" LOC = "F12" ; NET "Switch_GPIO_in" LOC = "G12" ; NET "Switch_GPIO_in" LOC = "H14" ; NET "Switch_GPIO_in" LOC = "H13" ; NET "Switch_GPIO_in" LOC = "J14" ; NET "Switch_GPIO_in" LOC = "J13" ; NET "Switch_GPIO_in" LOC = "K14" ; NET "Switch_GPIO_in" LOC = "K13" ;

This problem is realy getting annoying, there must be something essential I have been overlooked.

Reply to
Raymond Bakken
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Reply to
Aurelian Lazarut

Did you already compared your mhs and mss files with the original one? I think the answer for your problems can be found in these files.


Reply to
Frank van Eijkelenburg

Hi Raymond,

Something I ran into once while doing something similar: remember that the GPIO component is bi-directional by default. You can statically configure a particular GPIO block to be always-input or always-output, but otherwise it's configurable by software (on a per-bit basis). The BSB may have defaulted the LED and Switch GPIOs to be outputs and inputs respectively, because it knows what they are.

If you haven't already thought of this, try adding the following lines before your while loop:

XGpio_mSetDataDirection(LEDS_BASEADDR, 1, 0x00); /* all outputs */ XGpio_mSetDataDirection(SWITCH_BASEADDR, 1, 0xff); /* all inputs */

Alternatively, you could fix it in hardware. Or, of course, it could be something else entirely... :-) Hope this helps.



Reply to
Ben Jones

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