Hi !
In the spartan datasheet I can read that:
"Horizontal routing resources are provided for on-chip
What does partitionable mean in this case ? Does this mean the horizontal lines can be divided ? If so, where (how many) the division points are there ?
Is FPGA Editor removed from ISE6.1i ? I've recently used 6.1i at my university, and couldn't find it :(
Every 4 CLBs, the horizontal tristate line has a pip, delivering the partitioning you read about. Only one of the four horizontal lines has a pip at each CLB column giving a staggered partitioning. Those lines can also interface with the IOBs on the left and right side of the device. They aren't "real" tristates in that if you drive a 1 and a 0 into the same line, the chip doesn't complain with smoke and heat - it gives you the low logic level.
FPGA Editor is in the 6.1 tools, but I understand it's not a WebPack item. (I could be mistaken on this)
Thanks, this is exactly what I wnated to know.
Yes, this info I've seen somewhere in the group archives.
Unfortunately it was the case - it was WebPack installed on this machine. I'll get access to full installation at university soon :)
Thanks !
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