AVNET's Spartan3 400 dev board & PCI

Hi, I'm tring to use my PCI core, with AVNET's Spartan3 400 evaluation kit. What value should have 'Drive strenght' & 'Slew rate' in constrains? Currently drive strenght is 12mA which is default for PCI33_3.3V. But betwen FPGA and PCI slot there are level translators 3.3V->5V, so maybe should be 24mA, or somethig else? Board's documentation states that, board is not 100% compilant to the PCI specification but should works in most systems. Anybody knows in what areas this board is not 100% compilant? And at which systems don't work? Currently I'm tring use it with BX based motherboard. And actually system don't boot up. When I've try on NForce3 chipset motherboard system have worked, but my board haven't been detected.

Best Regards Krzysztof Przednowek

Reply to
Krzysztof Przednowek
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We use bus switches in our PCI development boards and they are a good solution. You should not have to alter your drive because they are in series. A typical bus switch is usually represents a series resistance of about 5 ohm or less and generally does not have much effect. Timing wise most are quoted with a through propagation time of less than 250 pS.

As to compliance you probably find it is either the capacitive load, or the trace length from the connector that don't meet the specification. We have never seen or heard of an issue with our own boards when using bus switches in the PCI interface.

John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 PCI Development Board.

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Reply to
John Adair

"Krzysztof Przednowek" schrieb im Newsbeitrag news:dl4lej$ham$ snipped-for-privacy@inews.gazeta.pl...

1) does the board worj when you use Avnet ref design image ? 2) the 24ma would not help, you have some problem with your core that is the reason for the freeze
  • the 3.3 5V translators dont much matter
  • the not fully compliant most likely is also not a problem at all

! make sure you have "unused IOB FLOAT" in the bitgen options or some unused PCI pin may get pulled

and I suggest you start testing and analyzing some existing and working PCI design before trying your own, and for your own core make sure it works in testbench

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there is included a very simple PCI core that we have verified on several boards - I am pretty sure it would work as soon as you setup the .ucf pin locations properly


Reply to
Antti Lukats

John Adair schrieb:

The plain fact that there is a level translator present is a violation of the specification. Section "It is specifically a violation of this specification for expension boards to:

  • Attach any pull-up resistors or other discrete devices to the PCI signals, unless they are placed *behind* a PCI-to-PCI bridge."

This seems to be general consensus. The PCI-spec just is to old to foresee todays voltage level problems. When the spec was written they could not imagine any good use for discrete devices on the signals but they were allready seeing abusive use of discrete devices in prototypes. So the board forbid them.

Kolja Sulimma

Reply to
Kolja Sulimma

Hi, Thanks for answers.

There was no reference design for PCI included. But I believe board works. Everything else works fine. Currently I'm workin on some kind of PCI monitor, to see what is going on.

I think that is something with my core, too. I was asking about current, to be sure that electrical part of design is good.

I've try to test my core with Altera'a testbench from their evaluation version of PCI compiler... But they set clk and data and everything else in the same time. How it could posible to sample data on rising clk, when data are set up in the same time? And they use adresses (in config read/write) with oldest bit set, why?

Best regards Krzysztof Przednowek

Reply to
Krzysztof Przednowek

The board works fine for me anyway ... (tried it in two different PCI mother board both 5V and 3.3v)


Reply to
Sylvain Munaut

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