I'm working on a cpu core and intend to embed it into ASIC circuits, with the aim to do some network processing. Now the FPGA prototype is running and a 66M speed is achieved( xilinx virtexII-4 ). Wondering how fast it can run in ASIC, we had our ASIC guys to synthesize the codes and the result was shocking, it reached 400M! Far beyond our expectation of 150M. The library we used was of 0.13u, from TI, fairly fast, in which a NAND gate is around 0.03ns.
Now my question is: Is the ASIC speed result reliable? Since we didn't do P&R( we don't have tools and experiences ), I really doubt the timing report may be over optimistically estimated and not reliable. I was told something about "wire load model" and ours is automatically selected by the compiler.
Anybody can give me some hints or direct me to some documents will be very appreciated! Thank you very much.
yu jun
snipped-for-privacy@huawei.com