Hi All
I need a circuit or piece of equipment that will;
Produce a 100MHz clock signal locally, and distribute this to 16 50Ohm inputs. Or input a clock signal (5-200MHz) and output this to the same 16 channels. Has a jitter of less than 200fs. Vpk-pk = 0.4V min.
Tall order? I think so.
200fs is probably pushing it even for ECLinPS. See
for what you can do with reasonably off-the-shelf parts.
ON semiconductor also does GigaComm parts, which I've not used, but John Larkin has
It seems that they are appreciably faster (and more expensive). They were available off the shelf from Digikey but today Digikey didn't recognise the part number NBSG16VS - Newark did, but indicated zero stock and a 64 day lead time.
-- Bill Sloman, Nijmegen
What are the physical distances involved? If the distrib is box-to-box through cables, the 200 fs is unrealistic, although local pll regeneration at each destination would help. 200 fs is pretty thin air.
And I hope you mean 200 fs RMS!
John
It's board to board. Max cable length about 20cm.
Yes.
Thanks. I never thought of looking at them. They do seem to have v.fast parts, and have a 1:10 clock driver. I haven't studied the other bits yet, but this driver comes quite close to our ideal.
Even if the cables were RG-405 semi-rigid cable or Nexans Quickform 141 conformable cable with PTFE (Teflon) dielectric the attentuation for the high frequency components of your signal would be pretty high - Qickform 141 has an attentuation of 1.95dB per metre at 20GHz (corresponding to a transistion time of 8 psec).
You might do better with super-conducting cable, where the decreasing skin depth won't be quite as lethal, but it sounds very hairy.
-- Bill Sloman, Nijmegen
Would it be possible to use a VGA (or any other type of amplifier), and feed the output to a power splitter (eg. those ones from MiniCircuits)? Would the amp's noise add significantly to the jitter? How could I calculate this?
You shouldn't need to.
The best jitter you can hope to achieve is limited by the thermal noise on your logic signal as it sweeps through the threshold voltage.
If Gigacomm logic were to offer a 40psec 10% to 90% transition time on the 0.8V ECL voltage swing, you've got a slew rate of 16V/nsec.
Assuming that the logic gate has a thermal noise of 1nV/root Hz in the linear region (about the same as a 50R resistor) and a bandwidth of
16GHz (which roughly matches the 40psec transition time) you've got an RMS noise level of 125uV, equivalent to about 8fs of jitter, so you aren't attempting something that is totally impossible.You do have to bear in mind that anything that attenuates the 16GHz component in your clock edge slows the slew rate at the transitions, and increases the jitter in proportion.
If your VGA has useful gain at 16GHz, it might help, but it is also going to be amplifying any noise on the signal in the same proportion, which undoes most of the advantage.
-- Bill Sloman, Nijmegen
How about 200ps RMS? Is that what you mean? How, exactly do you intend to you intend to measure your 200femtosecond jitter?
No, 200fs. Measure it? We can measure the performance of the final system which will show the effects of the jitter. We can't directly measure the jitter.
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