A loadword and storeword instruction from sram, maybe 3 cycle and atomic operation, would really shrink a lot of AVR programs. Faster. Smaller Cheaper. Whats the chance of this happening? See thread on avrfreaks.
Yo Ulf S: How about a lds and a sts inst on the AVR?
Jun 16, 2010
4 Replies
They already have this, it's called an AVR32 ;)
-jg
Was about to give the same comment ;-)
Changes to the core might happen though. The new ATtiny20 has a reduced core with but 16 registers. The problem is decoding space. You need 5 bits for register address as well as n bits for the address. With RAM space growing to 16 kB, you will need 14 bits, so a total of 19 bits. Have to be a 4 byte instruction, which probably makes the instruction decoder unhappy.
Best Regards
Ulf Samuelsson
These are my own personal opinions, which may
or may not be shared by my employer Atmel Nordic AB
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D Thanks for the reply Ulf. Tell those other atmel guys to pay more attention to the avrfreaks. They think no-one empowered reads the questions.
The alternative is to send to the "avr at atmel dot com" mail address. BR Ulf
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