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Understanding connection between MCU and Flash memory

Hi,

I am a software engineer, with little experience of electronics, trying to understand some more hardware.

I am currently studying the schematics for Samsung's SMDK2410X built around an ARM9 S3C2410X CPU, more particularly how SDRAM and Flash are connected to the CPU (I'm guessing this is what I will have to configure first in the boot software I intend to write).

For SDRAM, the address and data lines are connected directly to the SDRAM chips, but for the (Strata) flash chips, there are intermediate chips for both the address and the data lines, of type Philips

74LVCH162245A (16-bit transceiver with direction pin).

I am guessing that these chips are used as latches, and that their use is related to some timing issues in the communication between the CPU and the flash memory.

Is this correct? Why aren't the 74LVCH chips necessary for SDRAM? Where can I find more information about that kind of designs (Google, books, etc.)?

I am also wondering if the use or non-use of these 74LVCH chips is assuming some particular timing or other configuration on the CPU side.

Thanks in advance for any useful information,

Best regards,

John

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Reply to
John Boblongo
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162245's don't latch. Any chance they're being used as voltage level translators? 
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Rob Gaddi, Highland Technology
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Reply to
Rob Gaddi

Hi,

chips, but for the (Strata) flash chips, there are

74LVCH162245A (16-bit transceiver with direction

related to some timing issues in the communication

find more information about that kind of designs

I can't speak for this arrangement specifically, but I have seen this on ZiLOG ZNEO boards - there, the explanation given was: The flash-chips are driving their output for too long even after that output was disabled. This would cause bus collisions in case the next CPU cycle happens to be a "write" to anywhere. The DRAMs are reacting faster when it comes to shutting up, so that little trick is not needed there.

I would assume that the same problem could be encountered in almost any design, since the ZNEO's 20 MHz clock is not exactly an earth-shattering speed (means: most other 16- and 32-bitters are faster and therefore more likely to face the same slow-flash issue).

Hope it helps,

Stefan

Reply to
Stefan Carter

Looking at the datasheets for CPU, SDRAM and flash, it looks like everything is running at 3.3 V. What am I missing?

Best regards,

John

Reply to
John Boblongo

This sounds like a satisfying explanation.

Thanks a lot, I was starting to get frustrated :-)

Best regards,

John

Reply to
John Boblongo

This sounds like a satisfying explanation.

Thanks a lot, I was starting to get frustrated :-)

Best regards,

John

Reply to
John Boblongo

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