TILE64 embedded multicore processors - Guy Macon

In article , snipped-for-privacy@mojaveg.lsan.mdsg-pacwest.com (Everett M. Greene) writes: |> "Del Cecchi" writes: |> |> > And if you think that the speed of light has anything at all to do with |> > the propogation of signals on long wires on chips, you are even less of |> > an expert than I was giving you credit for. |> |> Say again? Since when is propogation delay /not/ a function of |> the speed of light?

Since Maxwell. Look up "RC delay". It is well-known and simple enough for even Wikipedia to be reliable.

Regards, Nick Maclaren.

He is a typical Usenet flamer. The truth of his claim does not matter to him; it is merely a stalking horse for the actual payload, which is the embedded insult. This is not to say that he is nesesarralty wrong, of course; he will hang his insult on a true assertion if that is possible.

It is always interesting to analyze the convoluted logic of the Usenet flamer; first he fabricates a lie -- that I claimed to be an expert in semiconductor fabrication (repeating the lie again and again despite my posts and my resume clearly stating that I am an expert in board-level and system-level electronics, not wafer-level) -- then he flames me for supposedly making errors about the fine details of semiconductor fabrication, despite the fact that I freely admit that I have limited knowledge in that area and merely presented my calculations and asked in anyone sees where they are wrong. All in all, a typical pattern of behavior for a Usenet flamer. Mildly interesting in its way, but not the sort of thing that gets any veteran Usenet participant excited.

There is an interesting study that sheds light on the psychology of the Usenet flamer:

"The most hostile group was the one with high but unstable self esteem. These people think well of themselves in general, but their self-esteem fluctuates. They are especially prone to react defensively to ego threats, and they are also more prone to hostility, anger and aggression than other people.

"These findings shed considerable light on the psychology of the bully. Hostile people do not have low self esteem; on the contrary, they think highly of themselves, But their favorable view of themselves is not held with total conviction, and it goes up and down in response to daily events. The bully has a chip on his shoulder because he thinks you might want to deflate his favorable self image."

-Roy F. Baumeister, _Evil: Inside Human Violence and Cruelty_ p 149

I am still waiting for you to answer the questions I asked the first time you made the above claim. First you suggested a Google search that led to page after page that did not support your claim, and now you reference a Wikipedia entry that does not support your claim.

Please reveal what you believe the propagation velocity of a signal in a chip-scale semiconductor interconnect to be, how you derived that speed, and why you believe it to be unrelated to the speed of light. The only references I have been able to find say that the velocity is about 70% of the speed of light in a vacuum.

Reference:

(Please note that I am not claiming any expertise in this area, just that your assertions are not supported by the references you cite.)

In article , Guy Macon writes: |> |> >> Say again? Since when is propogation delay /not/ a function of |> >> the speed of light? |> >

|> >Since Maxwell. Look up "RC delay". It is well-known and simple |> >enough for even Wikipedia to be reliable. |> |> I am still waiting for you to answer the questions I asked the |> first time you made the above claim. First you suggested a Google |> search that led to page after page that did not support your claim, |> and now you reference a Wikipedia entry that does not support your |> claim.

I think that you have confused me with someone else; as far as I can recall, this is my first posting on this matter.

Secondly, I said that Wikipedia would be reliable on this matter, not that it would be useful. It isn't :-)

|> Please reveal what you believe the propagation velocity of a signal |> in a chip-scale semiconductor interconnect to be, how you derived |> that speed, and why you believe it to be unrelated to the speed |> of light. The only references I have been able to find say that |> the velocity is about 70% of the speed of light in a vacuum.

Why? I am not a physicist, and was puzzled by the same question. But what I asked was for pointers to references (e.g. books) where I could read up about it). I did so. I recommend that you do the same. No, I can't remember which ones I read.

Regards, Nick Maclaren.

Indeed I have. Please accept my apology. It was Kai Harrekilde- Petersen who made the previous comment. Please disregard what I wrote, which was a reply to his comments mixed with yours due to my error in thinking that the same person wrote both. Sorry about that.

Dear me, Guy: you really appear to be not only an idiot but a compulsively persistent one (now, *that's* a 'personal attack', just so you understand the difference between one and what Del offered).

The facts are simple: you made an unequivocal assertion in a technical forum in an area well outside your realm of competence that Del (who almost certainly knows infinitely more about the subject at hand here than you do) considered asinine, and given your rather grandiose claims to expertise on the Web page that you link to in your sig he hauled you up short. Ever since then you've been frothing at the mouth whining about that 'personal attack' and making wild observations in return about someone about whom you clearly know absolutely nothing.

...

No, you moron (once again, notice the difference between this and what Del offered): you claimed to be "an expert in all areas of electronics" (of which electronic signal propagation under varying conditions certainly qualifies as one aspect). Since you don't seem to claim English as one of your areas of expertise perhaps you aren't aware that your subsequent phrase ("including...") dues not serve to limit that earlier sweeping claim but instead merely offers some examples. Well, now you know better, and why Del's comment was entirely appropriate.

So please shape up or shut up: no one here is likely to take you anywhere nearly as seriously as you take yourself, but you could at least stop acting like an injured adolescent. Gee - you don't suppose that being 'self-taught' has left you feeling the kind of 'unstable self esteem' that you just implicitly accused Del of, do you?

- bill

ahahaha... What is it about all of you geriatric know-it-all geeks in the comp.arch newsgroups? You don't get enough fiber in your diets, is that it? ahahaha... You, Cecchi and Maclaren are chicken-shit flaming idiots. How about that?

ahahaha... AHAHAHA... ahahaha...

Louis Savain

Why Software Is Bad and What We Can Do to Fix It:

from fundamental circuit principles of rlc transmission lines. for each segment, trise is 0.7RC.

The resistance of on chip interconnect is high enough that it swamps the inductive reactance.

So, look up the values for resistance and capacitance per micron or per millimeter for copper wires of width of say .2 microns and thickness of maybe 0.5 micron.

You will find that the speed of light doesn't enter in to it.

del

ahahahaha... The speed of light and the Planck constant are a fundamental part of everything, especially signal propagation speed.

Louis Savain

Why Software Is Bad and What We Can Do to Fix It:

Douch your brain Traveler as it is full of shit.

^^^^^^^^ douche

... ...

Inferring that a (hopefully purposely) shorted clump of deep sub-micron copper splinters, with widths on an order similar to the mean free path of an electron, will behave similarly to a transmission line seems to be a bit of a stretch. Ask the people doing parasitic field extraction and Elmore delay models whether they should even be called "wires", other than for legacy reasons, at today's technology nodes.

There are also good reasons why those 10 (and very possibly many more at 90nm) buffer insertions are desirable. The answer to why might give you a better handle on typical long wire delays in ICs these days, and why they might be a problem.

IMHO. YMMV.

-- rhn A.T nicholson d.0.t C-o-M

In article , "Del Cecchi" writes: |> |> So, look up the values for resistance and capacitance per micron or per |> millimeter for copper wires of width of say .2 microns and thickness of |> maybe 0.5 micron. |> |> You will find that the speed of light doesn't enter in to it.

When I played around with the formulae, I found that, to a first approximation, the delay was proportional to the aspect ratio of the wire. I was surprised it was quite that simple, but it was.

That, of course, explained most of the effects that were puzzling me about problems with process shrinks - e.g. a MERE shrink gives essentially no performance advantage, but only a moderate amount of reengineering is needed to get quite a lot.

I would have to spend at least a few months learning physics before I could even begin to understand leakage and other losses on that scale - so I rely on asking colleagues who know more ....

Regards, Nick Maclaren.

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R>Inferring that a (hopefully purposely) shorted clump of deep

Thanks! I was expecting some sort of explanation such as the above, based on the premise that if the tiny traces on an IC don't act the same as the much larger traces on a PWB, it would pretty much have to involve something that is different between the two, as opposed to simply claiming that an RC filter slows down the propagation of a signal in both cases. Much appreciated.

Needless to say, I have been doing web searches on this, and the phrases "Elmore delay" and "parasitic extraction" turned up some real treasures:

_The Future of Wires_

_The Wire_

Parasitic Extraction and Performance Estimation from Physical Structure

I also found this in an abstract (the actual paper isn't online):

A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency

"We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity- of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18 µm CMOS process. Transmission-line- style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum.

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Del Cecchi wrote:

I am not sure what you are getting at. Are you saying that the risetime figures of a lowpass RC filter are related to signal velocity and propagation delay?

Chip-scale may be a different animal (and if so I am willing to learn the differences), but I believe that, at least at the board level and system level, limiting the risetime (or, to be precise, rolling off the high frequency response -- an RC filter is not the same as a slew-rate limiter) leaves the propagation delay at the same large fraction of the speed of light in a vacuum as before. The series of RC low-pass filters would certainly limit how *far* a high frequency clock can travel before being attenuated to almost nothing and needing a repeater (and of course a repeater has its own delay), but my understanding is that it doesn't change how *fast* it travels.

BTW, I found an abstract (Alas, no full text) that puts some numbers on the propagation speed and line length that can be achieved:

A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency

"We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity- of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18 µm CMOS process. Transmission-line- style interconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-light data transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum.

Again I am no expert, but it seems to me that the signal velocity and maximum length of a repeaterless interconnect on a 0.9 GHz 0.90 µm TILE64 would be at least as long as the signal velocity and maximum length of a repeaterless interconnect on the 3 GHz 0.14 µm device described, and quite possibly a lot longer.

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Guy Mac>Again I am no expert, but it seems to me that the signal velocity

Sorry. Typo/brainfart. The TILE64 is 90nm, not 0.90µm.

Rise time is not propogation time. Rise time only adds to the propogation time.

For a zero-length circuit.

No point in getting worked up about flamers like little Billy here.

"Usenet being what it is, if you participate in newsgroups at all over a period if time you have the possibility of attracting your own personal lunatic, who considers any disagreement a personal affront, and considers it their duty and obligation to "expose" the person they fixate on. It's kind of pathetic, but they can't quite seem to figure out why no one else sees their actions as heroic." -Richard Ward

Also, Nick Maclaren didn't flame anyone. He has been the ideal technical newsgroup participant; discussing technical issues in such a way that reading his posts usually leads to learning something new. I confused him with another poster in one of my posts, a mistake that I am very sorry for making.

Del Cecchi to have decided to have a reasoned discussion about technical issues without making personal comments as well. I was very glad to see this and hope in conynues, because he seems to know a lot about the topic under discussion.

In article , Guy Macon writes: |> |> BTW, I found an abstract (Alas, no full text) that puts some |> numbers on the propagation speed and line length that can be |> achieved: |> |> A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency |> |> "We successfully show the practical feasibility of a purely |> electrical global on-chip communication link with near velocity- |> of-light delay. The implemented high-speed link comprises a 5mm |> long, fully shielded, repeaterless, on-chip global bus reaching |> 3Gb/s/wire in a standard 0.18 µm CMOS process. Transmission-line- |> style interconnects are achieved by routing signal wires in the |> thicker top metal M6 layer and utilizing a metal M4 ground return |> plane to realize near velocity-of-light data transmission. The |> nominal wire delay is measured to 52.8ps corresponding to 32% |> of the velocity of light in vacuum.

There has never been any difficulty in producing a few wires that cross the chip. You will note that modern general-purpose CPUs need wires up to 4 times longer on processes that are 3 times smaller, and that the above trick doesn't allow wires to cross. Del might be able to say whether the word 'practical' is misleading or just plain wrong, but I am damn sure that it is one or the other.

Regards, Nick Maclaren.