TILE64 embedded multicore processors - Guy Macon

|> > It is a marketing document, describing various "innovations" |> > without revealing basic architectural details such as how the I/O |> > is connected to the cores, how wide the data paths are, or |> > what the instruction set looks like. |> >

|> I would consider the width of data paths an implementation artifact, not |> part of the architecture. In fact, how the I/O is connected is probably |> also an implementation artifact.

Depending on how deeply they are built into the specification, of course. In some architectures, the instruction set is itself an implementation artifact - and sometimes even a customer configurable one, at that!

If, however, the document refers to the great merits of those things, then it is fair to damn it for not giving any information on them, whether they are architecture or implementation.

Regards, Nick Maclaren.

I just went back and looked at the documentation for MIT's RAW processor, which later grew into the TILE64, half-remembering that it had a torus topology. That, along with the repeated claim that every tile in a TILE64 connects to four neighbors, led me to believe that the TILE64 is toroidal. Looking back at the RAW, I found the same "every tile connects to N tiles" claim, but I also found a claim that it took "six hops corner- to-corner" on a 4x4 array, so I must conclude that the RAW

-- and presumably the TILE64 -- does not have a toroid topology.

I sent an email to Tilara asking for a clarification. I will post the answer when and if I get it.

Why would you think that? It seems to me that The whole point of the architecture seems to be to avoid elements that grow at a faster rate than the number of cores as you scale up to more cores. A wire across the width of a die isn't all that bad, and as recent discussions in this thread have shown, clever interleaving can keep the wires quite short.

You claim on your page "I am an expert in all areas of electronics, including analog, digital, microcontroller, high-power, low-power, high volume, aerospace and consumer electronics."

And you then say "a wire across the width of a die isn't all that bad".

Sorry. bzzt. thanks for playing.

As usual, the person who resorts to personal attacks is the person who hasn't done the math. There are a couple of notable exceptions here, but it's a good general rule of thumb for evaluating competence.

Both are true statements. If you doubt the first, I suggest staying off of commercial or military aircraft until you get a list from me of which ones have safety-critical components that I designed and which ones have safety-critical components that were tested with test systems that I designed. The TILE64 runs at 600-900 MHz.

It takes one clock cycle to move data to the next tile.

With an 8x8 edged array, the worst case is 14 hops (14 clock cycles) to propagate data to the farthest tile.

With an 8x8 toroidal array, the worst case is 7 hops (7 clock cycles) to propagate data to the farthest tile.

Tilara won't reveal how big the die size is, but an 4-core Intel Core 2 Extreme QX6850 is 17x17mm and an Intel 80-core terrascale processor is 16.5x16.5mm

Let's be conservative and assume that assume the TILE64 is almost 4x the area. Let's say 29.9792458 x 29.9792458 mm...

The speed of light in a vacuum is 299.792458 millimeters per nanosecond. In semiconductor wiring it's about 70% of that, so let's be conservative and assume 50%. And let's bump that 900MHz up to 1GHz (1 nanosecond per hop). That makes the propagation delay across the chip

Guy, I believe Del is talking about the fact that current "wires" aren't normal wires at all.

Sub-100 nm processes makes it more or less impossible, afaik, to simply lay out a long wire, you need a bunch of active components to transport a signal that far.

Terje

And, has been pointed out to you, a clever

In no particular order.... I was the one that pointed out that wrapping all the way across the chip to complete the torus was stupid and unnecessary. So reminding me of that was redundant.

And if you think that the speed of light has anything at all to do with the propogation of signals on long wires on chips, you are even less of an expert than I was giving you credit for.

I wasn't disparaging you with the quote from your resume. I wasn't even "personally attacking" you. I was merely pointing out that in this case your demonstrably wrong assertion about wires was in conflict with your asserted expertise.

Comp.arch is sort of a risky group in which to be making assertions of universal expertise, even indirectly via link.

del

Mr Macon, may I humbly suggest you do a search on the term "RC transmission line" before venturing further?

Sincerely yours,

Kai

That's interesting. I wasn't aware of that. The TLE64 is 90nM.

The rule of thumb that I have seen used is that wiring delays on a VLSI semiconductor are roughly 70% of the speed of light in a vacuum. That would obviously be a run short enough to be just a wire. Do you have an estimate for how fast signals propagate over long runs with many active repeaters?

And to head off Del Cecchi's next personal attack, the list of what I am expert in (analog, digital, microcontroller, high- power, low-power, high volume, aerospace and consumer electronics) does not include semiconductor fabrication, so he should not be surprised if i don't know some details of an area where I have no expertise.

Really? Care to point out the place where I claim expertise in the fine details of semiconductor fabrication? I thought I had made it quite clear that I design with ICs but do not design ICs.

As for your assertion that you were "merely pointing out" various flaws that you believe I have and not engaging in a personal attack, I will refrain for "merely pointing out" certain things about you, and merely express my preference for straight-talking flamers over flamers who hide behind passive-aggressive weasel words. Better still, of course is sticking to the topic at hand without any sort of personal comments at all.

I insert a plea here for more diplomacy on Usenet, regretfully absent since the 'commercialization' of the Internet and the demise of UUCP networks.

Is Del Cecchi related to the famous Al Cecchi of Northwest Airlines fame?

As for chip scale transmission lines, I found this short article illuminating:

Regards,

Michael

Digital design normally includes stuff like that. Better would be then not to include a link to your resume, where the claims reside. If I were flaming you, you would know it.

Sorry, no relation. And Al spells his name Checchi. So if we are related it is distantly, back in the old country. Too bad, I could have used some free tickets.

And what does one do when correcting someone who is making assertions that are incorrect.

del

That *is* interesting! I always wondered how chip-scale transmission lines differ from the pcb-scale transmission lines that I am familiar with.

Searching further, I found:

The last URL appears to show that a wire all the way across a 700 MHz

----------------------------------------------

Kai Harrekilde-Petersen wrote:

OK. I just did. What were you expecting me to find? I have lots of experience with the usual large-scale transmission lines (coax, ecl logic. microstrip, etc.) but not with wafer- scale transmission lines. Is there something about the latter that invalidates my calculation of the propagation delay across a TILE64 being less than the delay that it takes data to hop to the next cell? The above URLs seem to be saying that they are about the same. Is the "70% of C" rule-of thumb wrong?

Discuss the issue at hand rather that engaging in repeated personal attacks and in general acting like a hormone-soaked geek butting heads with a rival geek during geek rutting season?

Do the math yourself and explain where I went wrong when I did the math? Do you think I got the speed of light wrong? Did I get the wrong percent reduction from C typical of microprocessor interconnects? Did I get the size of the die wrong? The amount of time it takes for data to hop between TILE64 tiles? Simply asserting that I am incorrect again and again interleaved with passive-aggressive insults does nothing to show me where my calculation was wrong.

Present evidence and logical arguments?

Pay attention to what others are telling you, such as "I insert a plea here for more diplomacy on Usenet?"

Make sure that it isn't you yourself who is incorrect?

Not tell outright falsehoods such as answering the question "Care to point out the place where I claim expertise in the fine details of semiconductor fabrication?" with "your resume, where the claims reside." when said resume contains no such claims?

That *is* interesting! I always wondered how chip-scale transmission lines differ from the pcb-scale transmission lines that I am familiar with.

Searching further, I found:

The last URL appears to show that a wire all the way across a

Tilara won't reveal how big the die size is, but an 4-core Intel Core 2 Extreme QX6850 is 289 sq mm and an Intel 80-core terrascale processor is 273 sq mm so I am guessing 200-300 sq mm for TILE64 The TILE64 runs at 600-900 MHz and it takes one clock -- 1.11 to

I called on of my clients who does a lot of high-performance computing and asked them if they were willing to buy one of the TILE64 boards and have me evaluate it. They gave the OK so I contacted Tilara sales. Three days later, no reply.

Do I smell vaporware in here?

Perhaps not the "whole point", buy certainly a key point. Since you brought up Raw, I'll cheat a little and just quote the Raw Spec.

"The Raw design philosophy argues for an array of replicated tiles, connected by a low latency, high throughput, pipelined network.

This design has three key implementation benefits, relative to existing superscalar and VLIW processors:

First, the wires are short. Wire length has become a growing concern in the VLSI community, now that it takes several cycles for a signal to cross the chip. This is not only because the transistors are shrinking, and die sizes are getting bigger, but because the wires are not scaling with the successive die shrinks, due to capacitive and resistive effects. The luxurious abstraction that the delay through a combinational circuit is merely the sum of its functional components no longer holds. As a result, the chip designer must now worry about both congestion AND timing when placing and routing a circuit. Raw's short wires make for an easy design."

The problem is that the signal will not propagate across the die without buffers in the line. For example one wire across 16mm 0.13u die needs ~10 buffers with 200MHz clock to propagate cleanly, and those buffers slow down the signal ~60-70ps each. And smaller processes are even more problematic.

--Kim

Thanks! I had heard about the need for buffers, but that's the first time I saw any numbers. I ran into this:

Here are my calculations with ten buffers added:

Tilara won't reveal how big the die size is, but a 4-core Intel Core 2 Extreme QX6850 is 17x17mm and a 80-core Intel Terrascale processor is 16.5x16.5mm, so let's be conservative and assume that the TILE64 is almost 4x the area. Let's say it is a nice round number: 29.9792458 x 29.9792458 mm. BTW, the TILE64 is fabricated as 90nm CMOS.

The speed of light in a vacuum is 299.792458 millimeters per nanosecond, so a light beam would traverse the above die in 0.1 ns. The actual velocity in semiconductor interconnect wiring is 70% of C, so it would take 0.15 ns to get across the chip if there were no buffers.

The TILE64 runs at 900 MHz and it takes one 1.11ns clock to move data to the next tile in the 8x8 array. The worst case is 14 hops corner-to-corner -- 15.55ns. With a toroidal topology, the worst case is 7 hops -- 7.77ns.

Depending on interleaving, to get a signal across a TILE64 die in order to get a toroidal topology would cost 0.36 or

I am still waiting for an answer from Tilara concerning the actual topology of the TILE64. My best guess is that it is the same as the RAW, which is an edged array. I have a client that is fortune 500 company and is willing to buy a development board and have me evaluate it, but so far I have not been able to get Tilara to sell me one or even respond to my inquiries. :( Could it be that they are in the business of attracting investors instead of customers?