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SPI with master at each end

My target platform is an ARM-7 with an SPI connection to an FPGA. I need either device to be able to initiate data transfer, the approach I'm considering is to use a single additional data line from the FPGA to the ARM, "FPGA data waiting". When the ARM is notified of data waiting to be pulled back, it will initiate a rotation. If there happens to be data ready to go both ways, then the single rotation will handle both of them. Potentially fairly neat, aside from possibly the handshaking.

I'd appreciate any thoughts on my proposed approach. Is there a better / more standard way to do this? Does it have a name so I can hunt up an existing implementation?

Reply to
Bruce Varley
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Reply to
srl100

This doesn't sound like a dual master. In SPI terminology, the master is the device that drives the clock. In every SPI transaction, both the master and the slave can send and receive data (hence the MOSI and MISO pins).

So you just need to set the processor up as a plain old master, make sure the MISO pin is connected, and make sure you interpret the incoming data correctly.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com
Reply to
Tim Wescott

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