Re the earlier thread about T89C51RD2, and DIP replacements,

I see Atmel have just posted the August iteration of the AT89C51RD2/ED2 data sheet. In June they added DIP40, now they have PDIP40 for ED2 only, and the PDIP40 shows an order code. DIP40 looks like a ceramic package, and has no order code, so may have been a 'temp qualify pathway'.

They have also hiked the fMAX to 60MHz X1 / 30MHz X2. (was 40/20) Given that 22.1184MHz (& 24MHz) are widely used Freq, stopping at 20MHz for X2 was not a great idea.

... but to keep you on your toes, T89C51RD2 EE users need the AT89C51ED2, _not_ the AT89C51RD2 (no EE)


Reply to
Jim Granville
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FWIW, I've run the AT89C51RD2 part @ 24Mhz in 6 cycle mode for weeks on end and it continues to keep running. Not going to ship it that way, but it does show there is headroom in the product.

If you don't need all 64K of flash, you can use flash for storage in a per byte boundary (it does not require an erase first) and just use the top 2K or so of the 64K region. Unlike the T89C51RD2, the boot loader is ROMd in the device and doesn't require parallel programming of it in codespace. And the read/write cycles for the RD2's flash are the same for the ED2's EEPROM.


Reply to
Neil Bradley

BTW, did you get your divide timing or else the looped bresenham going within the time budget?


Reply to
Jonathan Kirwan

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