I'm interested to know if anyone has successfully programmed a Xilinx XC9500XL CPLD with a PIC18F using the Xilinx JTAG/TAP port. I've been reading Xilinx app note 058 and it looks feasible. The inbound data stream (SVF or XSVF file) would be coming into the PIC18F via a USB connection. This is for the purposes of occasional field-upgrades, not the frequent reconfigurations you would have with an FPGA using the USB & PIC combination to eliminate its boot PROM.
- posted
18 years ago
-- Rob