I2C Maximum Number of Slaves

Isn't there an I2C buffer/repeater out there?

I'm sure there are others.

each

kill

I'll use one if I have to but I'd like to know what each I2C chip adds to the capacitance. The documents state an input capicitance but I don't believe that is it.

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There will be some capacitance contribution from the interconnect. What are you using? Wire or microstrip? What sort of connectors? Getting accurate answers may be quite difficult, but you should be able to get a rough answer by search on t'Interwebs.

With a round trip of 2*125*5 inches (~= 32 metres) your data rates are going to be real sssssslllllloooooowwwwww.

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would

to

are

Some will be in parallel so the distances won't be to bad. My question is with the individual slaves and how much each chip adds to the capacitance. I can add a buffer but how many will be required?

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Why wouldn't you believe the datasheets? Do you believe the other specs. you can read there? Anyway, input capacitance of the IC is pretty low - it's the capacitance of your datapath that will cause troubles.

OK- let's throw in some numbers. I2C standard for 100kHz bus defines 1uS maximum rise time. Let's take a PCF8574 for example. Output current is specified as 10mA min. so at 5V it's about 500 Ohms. Let's take standard 510Ohm resistor. To get 1uS risetime, you can load the line with max. 1.9nF and still be in specs. What will cause the problems is the following - slowing down rise time increases the risk of noise pickup, as the transition from 0->1 is prolonged. So, even if your rise and fall times are within specs, long lines will most likely pick-up external interference, and as the I2C bus is edge-triggered you'll have a lot of problems.

To summarize - if you need long I2C bus use repeaters and keep the rise/fall times of every stub WELL within the specs.

to

it's

maximum

as 10mA min.

cause the problems

pickup, as the transition

specs, long lines will

edge-triggered you'll have

rise/fall times of every

I wasn't sure how much the input capacitance of the chip has on bus capacitance. Any idea on how to determine the number of SCL and SDA resistors that will be needed?

Thanks for your help!

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Did you read what I wrote a post before?

I didn't notice the max load line of 1.9nF. Thanks for your help.

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=A0 =A0 =A0

Speed vs. capacitance

Higher cap load. slower the speed,

If I remember it well, i2c does not require min-clock period,

If that's true, that mean you can have 1 day long pulse and you can have max number of slave - 125 or 127 devices attached to the bus

cheers,