I haven't run any tests that ran for loner than three weeks. I saw a maximum of less than 1% over a period of weeks. I didn't see a 1% drift every few nanoseconds. If it did have a 1% variation after only a few nanoseconds it could show a jitter of 100ps on that 10ns of code but I have no evidence that it changes that fast.
Many people have reacted to the 300ps latency to sync nodes as it faster than what they are used to. The fact that it will vary by only a few picoseconds is in line with everything else tested.
Sure. You sync to changes. The pulse kick timing is subject to probably less than the 1% variation on that 10ns of code from pulse to pulse than over a total of 10^15 cycles in a test. I have seen no reason to suspect that the driving pulse cannot tolerate that much variation. I think it a tempest in a teacup. If it were that hard to drive an xtal then all those simple circuits with cheap transistors would have the same problem.
I don't know what hardware you think you are describing. I am beginning to get a sense that you are not talking about the hardware that original poster asked about. When there is no clock to drive the design there is also no PLL or PWM hardware connected to the non-existence clock circuit.
Yes. He imagines something terrible like 20-80% and his simulations suggest that wouldn't work when he assumes it is that bad. I wonder what results he would get with
51% and 49%, I am used to seeing something very close to 50% so I hadn't imagined concerns over other things being between 20% and 80%.Sure. Simulations are fine, but if you make the wrong guesses about things like where the sense threshold is the simulation may not do what the real chip does.
For twenty years I have been working on the develop of these sorts of chips. You have to do lots of simulation in the development process before you can make chips so you can't start by testing the chips. To make the whole process work you have to get the simulation to be accurate as possible to reduce chances that actual hardware may not work. We have things close enough that all the designs in the last few years have worked as predicted by simulation.
You can't get accurate enough numbers from other people to simulate the effect of things like the package will have on pads. So all you can do it make it and test it. You test the last one back from fab. You can't give the results of tests on chips with foundry, design, or package changes while the chips are in fab and are not yet packaged. You can predict a lot of things but the exact result of what the foundry and package house actually did always has to be tested.
We developed all the software for 4OS and the Internet Appliance at iTV in the bit level simulator on the PC and dropped a working application into the FLASH memory when chips came back from FAB and were tested. So I like simulations since they don't have the observer effect problem with probing things in the real world. All the ROM code on these chips was developed in simulation before the chips were made.
A logic analyzer won't show the circuit from the pin that starts the processor running at full speed in 300ps. That's internal to each processor ith one and not a circuit you can probe with hardware. Of course we had to make tests circuits with on-chip probes long ago to characterize these circuits and fine tune cad simulation.
Years ago we looked at a different chip as it was running in a scanning electron microscope. You could see individual transistors switching but you really couldn't measure the number of picoseconds of jitter on a
300ps internal circuit.I have no idea how much variation in time take place in a
300ps transistor circuit from one switch to the next. Words like small, large, and very large are pretty meaningless. 5% sounds absurdly large to me but 15ps doesn't sound like a "very large" amount of time. You are free to make a value judgment that a couple of picoseconds sounds like a large amount of time to you.My experience is that most people get argumentative when you go from milliseconds and microseconds in embedded computing to talking nanoseconds, and many people object when they start hearing discussions of picoseconds. And you are the first person to tell me that a couple of picoseconds is a long period of time.
With the danger of spinning further of subject I will say that rickman's SPICE simulations are fine. However the history of this whole project, for twenty years, has been designing and building circuits that SPICE says can't work. What was said almost twenty years ago was that SPICE has to be tuned down by about an order to magnitude to be able to predict what the circuits that come out of the fabs will actually do and the characterization that the fabs provide themselves are not very accurate. The fabs love FPGA because they use them to calibrate their own processes as best they can.
By working out where it was in error it was possible to get closer to the actual limit of the silicon. When we made a
500MHz processor in the 90s without pipelining or cache and in .8u CMOS we were told by SPICE and many chip experts in top companies around the world that we were off by an order of magnitude in our estimates and that 50MHz was the best we could expect to work. The experts on usenet said the same thing. We had lots of proof that SPICE said 50MHz was possible in .8u but that 500MHz was impossible. They would say, "Do you realize that Intel was only able to get 64MHz in .8u even with deep pipelining and cache?" Sure.Some of the companies where these SPICE experts worked, besides our own, contracted for consulting to raise the skill of their designers and many licensed patents that were developed and that they wanted to use.
It was fun to then ask how it was possible for the person at that desk to be surfing the internet using an internet appliance using one of the chips that SPICE said could not possibly run at all. We have seen that on several generations of designs so I just warn you that SPICE isn't the last word on the subject, working circuits are.
We have learned how to tweak SPICE to get results that are closer to what our simulator predicts and to what the actual circuits do. But thinking that SPICE can simulate what goes on in the circuits inside of the chip is an error.
Since the new parts are not available yet people have only been able to place advanced orders. If they have something they need to know now they can ask and we can say what we have seen on the last version of the chip and what we expect. If it is something important attention will be paid to it.
I can say is that I never saw more than 1% variation in pulse timing over 10^15 cycles in a test. To me that says that things don't change more than that from one cycle to the next so I think concern about that is misplaced. I have also seen a threshold very close to 50% so again I think concern that it might be anywhere from 30% to 70% or from
20% to 80% also seems like misplaced concern.I will run some threshold tests to see how much of an issue it is and we can see what simulation says with those numbers.
Best Wishes