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Debugging Embedded Dram - Need Help

Hi - I'm attempting to debug a problem with an existing embedded controller board. The board uses a MC68020 and uses either 1 or 2 banks of 30pin simm memory. I think this is a 199? design. The board supports either

1M or 4M memory. The SIMM memory is configured to be accessed as a 16bit wide data bus. The 1M memory works OK, but there are read/write errors when using the 4M memory. I'm confident the 4M memory that I bought is compatible, as I've studied the datasheets for both 1 and 4M and their topologies and access speeds are the same. No parity is used in this design. Refresh (
Reply to
Jim Flanagan
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Could the refresh counter be too narrow?

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

I'm sorry, I don't understand what you mean by 'too narrow'? According to the 4M datasheet, using CBR should take no more than 64mSec or 15uSec per column, assuming a square matrix (2^11). I see the refresh counter performing a refresh cycle about every 12uSec. So, I should be OK, or am I missing something? Thanks for the input. Jim

Reply to
Jim Flanagan

Check the actual number of columns. Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
Reply to
Spehro Pefhany

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