Cortex M4 Floating Point Size

Don't know about specialized FP DSP-s, never used one. I have been doing a lot of DSP-ing on a power (PPC) FPU (mostly on an MPC5200B). It has 32 64-bit FPU regs and can do MAC at both 32 and 64 bits precision. It takes 1 cycle/32 bit MAC and 2 cycles per 64 bit/MAC. Reaching that is not straight forward as on a DSP though, there are data dependencies to take into account. OTOH, having 32 registers can save a lot of load and store during the filter loop, I managed the 2 cycles/MAC in a loop at about 10% load/store etc. overhead penalty. Here is how I did it (VPA macros, self explanatory enough though):

Without going through that instead of 5nS/MAC I was getting 30nS/MAC in a plain loop, to be expected really as the pipeline is 6 stages IIRC.

Well of course, the thing with "normal" 32 bit processors is that they do not have 64 bit accumulators and 32 bits is nowhere near sufficient. 64 bit FP, OTOH, is quite handy. Especially on the power architecture FPU, where one can read 32 bit FP data and have these expanded to 64 bits in a single cycle.

Last time I had the fun doing this was on a CPU32 (on the 68340), quite a while ago :-). But the hardware FPU-s on the power architecture processors are really good at this, somehow they manage add/sub/mul within a single cycle.

Dimiter

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I know you don't really need the details but:

Most 32-bit FPUs use 8 bits for the signed exponent, one bit for the sign, and this leaves only 23 bits for the mantissa. Not 25. (There is also the hidden bit, of course.)

Just being pedantic.

Jon