CFP - High-level synthesis - Methodologies and Practice

========================= ========================= =============== Hindawi VLSI Design Special issue on High-level synthesis: Methodologies and Practice ========================= ========================= ===============

Call for Papers

--------------- Current VLSI technology allows the design of sophisticated digital systems with ever-growing demands in performance and power/energy consumption. Rapi dly changing user demands, unprecedented applications, evolved existing, or newly introduced standards, continuously shape the computational landscape .

It has long been observed that human designers' productivity does not escal ate sufficiently to match the corresponding increase in chip complexity. Th is technology-productivity gap is probably the most important problem in th e industrial development of innovative products. A dramatic increase in des igner productivity is only possible through the adoption and practicing of methodologies that raise the specification abstraction level, ingeniously h iding low-level, time-consuming, error-prone details. New EDA (Electronic D esign Automation) methodologies aim to generate high-performance digital de signs from high-level descriptions, a process called High-Level Synthesis ( HLS). The input to this process is usually an algorithmic-level description , generating synthesizable register-transfer level designs that can be impl emented on FPGAs or ASICs

We invite authors from both the academic and industrial communities to cont ribute original research articles as well as review articles that present n ew high-level synthesis methodologies and techniques or showcase interestin g aspects of their practice. Potential topics include, but are not limited to:

- Very high-level specifications and associated models of computation

- Challenges in high-level synthesis for heterogeneous manycore custom comp utation on FPGA-based platforms

- Imperative-, functional-, and concurrency-oriented domain-specific langua ges for hardware compilation

- Transparent optimization through code refactoring and source-to-source tr ansformations

- Intermediate representations for multistage transformation and optimizati on

- Link-time and interprocedural optimizations for improving whole program h ardware compilation

- Automatic compiler retargeting for efficient hardware generation

- New approaches for compiling dynamic languages to hardware

- Architecture description languages (ADLs) for automated hardware architec ture and toolchain generation

- Early assessment, design-space exploration, and analysis tools in the HLS environment

- Applying HLS for application-specific programmable processor generation

Before submission authors should carefully read over the journal?s Author Guidelines, which are located at

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elines/. Prospective authors should submit an electronic copy of their comp lete manuscript through the journal Manuscript Tracking System at
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according to the following timetab le:

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Important Dates

--------------- Manuscript Due: Friday, 2 August 2013 First Round of Reviews: Friday, 25 October 2013 Publication Date: Friday, 20 December 2013

Lead Guest Editor

----------------- Konstantinos Masselos, Department of Computer Science and Technology, Unive rsity of Peloponnese, Tripolis 22100, Greece

Guest Editors

------------- Steven Derrien, University of Rennes 1, INRIA Research Institute, Rennes, F rance Nikolaos Kavvadias, Ajax Compilers, Athens, Greece Hiren D. Patel, University of Waterloo, Waterloo, ON, Canada N2L 3G1

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