cache controller inner working

Hi,

I am confused about the following and appreciate any help.

Assume that a CPU generates read operation from the address say 0xAB3 and that the cache line size is 16 Bytes. Consequently we are looking for Byte 3 of the block 0xAB0. Assume that this address is not matched in the cache and has instead to be loaded from the main memory.

Is it up to the CACHE MEMORY CONTROLLER to generate 8 consecutive "lw" instructions ( one word is 2 Bytes): lw 0xAB0 lw 0xAB2 ... lw 0xABB

or instead generates one lw operation lw 0xAB0 and implictely the memory will send back the 8 words? how does it work in real system? and how the main memory is instructed to send the 8 bytes?

also how the cache controller recognise by itself the 3rd word? is there any counter

sorry if my questions seem so obvious but i am confused after reading two different textbooks and this is definitevly not a homework :)

thank you

Reply to
xu_feng_xu
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Following my question above, does the controller send 0xAB0 or instead0xAB3 followed by 8 consecutive lw

Reply to
xu_feng_xu

The implementation details depend on the architecture. Did you have any particular CPU in mind ?

Reply to
Arlet

Not one in particular, but want to see any real example if you can explain or have a link to pass i'll be gratefull

Assume the pentium processor

Arlet wrote:

Reply to
xu_feng_xu

Typically, in the case of a cache miss the cache controller will reload the whole cache line starting from the address aligned to the size of the cache line. The reads will be done in a burst using the full width of the memory bus. If the cache line was dirty (WB caching), it would be flushed into the write buffer before read and updated to the memory after the read is done.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

Hi,

Although the implementation might vary from processor to processor cache always works on 2 basic principle i.e. Spatial locality & temporal locality. So what that translates to is that ur cache controller will have to worry about the various cache write[Write through, write back, write combining etc..] and page replacement policies [LRU, random, MRU, round robin etc..]. Also the structure of the cache has an importatnt say in the way cache controller works [sets, associaitivity etc..].

So in short what a cache controller would do in general is bring a few of the nearby memory locations [ in this case addresses close to

0XAB0]. The prefetcher would take care of this [ Normally we deal in cache lines or in some cases we do prefetch split cache lines]. Thus it would be a hit in the cache. We would not have to worry about generating 8 consecutive "lw" in an actual machine.

-Akarsh

xu_feng snipped-for-privacy@yahoo.com wrote:

Reply to
akarshebbar

no "lw" instructions, only some bus cycles.

the whole cache line will be replaced.

the instruction cause cache miss will halt until the whole cache line is fetched into cache.

but I do know some architecture use software to fill the cache line. when cache miss, the cpu goto an exception handling. this machine has a special instruction to fill the whole cache line. the task of you software is to find a victim.

xu_feng snipped-for-privacy@yahoo.com wrote:

Reply to
dick

On a specific cache that I do know well (TriMedia) the cache controller generates a memory burst read request for 8 reads, each of 8 bytes, for a cache line of 64 bytes. In this case the cache-to-memory bandwidth is 8-bytes at a time. The burst request is actioned in the background over 8 cycles. If you look at the activity in each cycle you do indeed see 8 separate memory reads (memory-to-cache).

Note that the cache-memory bandwodth may be greater than the apparent memory bandwidth of the CPU-cache interface.

Chris ============================== Chris Bore BORES Signal Processing snipped-for-privacy@bores.com

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xu_feng snipped-for-privacy@yahoo.com wrote:

Reply to
Chris Bore

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