Hi,
I am confused about the following and appreciate any help.
Assume that a CPU generates read operation from the address say 0xAB3 and that the cache line size is 16 Bytes. Consequently we are looking for Byte 3 of the block 0xAB0. Assume that this address is not matched in the cache and has instead to be loaded from the main memory.
Is it up to the CACHE MEMORY CONTROLLER to generate 8 consecutive "lw" instructions ( one word is 2 Bytes): lw 0xAB0 lw 0xAB2 ... lw 0xABB
or instead generates one lw operation lw 0xAB0 and implictely the memory will send back the 8 words? how does it work in real system? and how the main memory is instructed to send the 8 bytes?
also how the cache controller recognise by itself the 3rd word? is there any counter
sorry if my questions seem so obvious but i am confused after reading two different textbooks and this is definitevly not a homework :)
thank you