BIOS that can skip memory test?

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I think -- and let me emphasize *think* -- that BIOS will stop its memory test as soon as it finds a "hole". If you could find some way to skip an address range between the real top of RAM and your stuff, I think that most BIOS will never find it.

Norm

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Thanks. I think you're right.

Our problem is that we want to use an off-the-shelf, commercial processor board with 512M memory, which is going to be one contiguous DDR module. We want to reserve the last 32M of the core memory for this pseudo-nonvolatile storage. So, I'm looking for some way to do it when there is no hole.

ISTR that this issue was discussed here, or maybe in sci.electronics.*, a while ago (meaning some time in the last two years) and the consensus was that even at warmboot, the motherboard chipset is completely reset - which interrupts RAM refresh. Therefore, you cannot rely on anything remaining in RAM across a warm-boot, even if the BIOS is fiddled with so it doesn't intentionally trash the upper area.

How is it forced to reboot?

Before testing the memory, BIOS initializes the memory and controller which causes the memory to lost its content. It might be impossible to do what you want. Why don't you store the logs in some nonvolatile memory, like a flash "key" or flash memory card?

Yes, it needs to first size the existing memory. So, good point.

First problem that comes to mind is that they probably don't want to incur the write-delays. There is always some kind of lag going on between the RAM buffers (which are sure to be destroyed on boot) and the flash writing process, which may be a bit behind. Particularly, if they need to write a lot of data quickly. I just went through a similar problem in writing high speed data logs to flash and had to give up and just use the extremely large RAM, because it was fast enough and the flash simply was not. They may really need the more recent information, in fact, for their post-mortems.

Use to be some old IBM PC cards had battery backed static RAM on them, when ISA bus memory was "the thing." Might be they need to set up something similar, though preferably on the PCI (going over the south bridge isn't optimal.) Perhaps take your suggestion, kind of, except modify the BIOS itself so that it saves the last known good RAM configuration to the CMOS timer/parameter chip (where the warm-start byte is also stored) and restore the chipset controller's arrangement on restart and without any destructive follow-up. Of course, you'd want BIOS source to poke away at.

Tricky.

Jon

Jonathan Kirwan wrote: : On Thu, 30 Sep 2004 08:42:52 +0200, "Grzegorz Mazur" : wrote: : :>Before testing the memory, BIOS initializes the memory and :>controller which causes the memory to lost its content. : : Yes, it needs to first size the existing memory. So, good point. : : Use to be some old IBM PC cards had battery backed static RAM : on them, when ISA

Easiest solution yes, if you can find a PCI memory card.

: [SNIP] arrangement on restart and without any destructive follow-up. : Of course, you'd want BIOS source to poke away at.

And the only BIOS source code that is (legally) in the public domain is the original IBM AT BIOS. Useless.

But then again, why not choose the path less traveled - implement the emebdded solution. That is, rid yourself of the BIOS alltogether and burn the Linux kernel plus minimalistic initialisation into the flash chip. Or use one of the Open Source BIOS replacement projects. Never done this myself, though...

Geir Frode Raanes S?rensen wrote: : Jonathan Kirwan wrote: : : On Thu, 30 Sep 2004 08:42:52 +0200, "Grzegorz Mazur" : : wrote: : : : :>Before testing the memory, BIOS initializes the memory and : :>controller which causes the memory to lost its content. : : : : Yes, it needs to first size the existing memory. So, good point. : : : : Use to be some old IBM PC cards had battery backed static RAM : : on them, when ISA : : Easiest solution yes, if you can find a PCI memory card.

Come to think about it - this might very well prove to be the only solution unless you can somehow prevent the hard reset line from beeing asserted. If not, then the memory controller will be reset no matter what software there is in the flash chip and memory content will surely be lost.

This is payback time for choosing COTS hardware...

Previous answers point out that this will probably not work, because the RAM contents are already gone before the BIOS even starts up.

To me, this sounds like the perfect excuse to finally buy a solid-state hard-disk (i.e. gobs of RAM forming a SCSI device).

... snip ...

That may be published, but it is not in the public domain. That fact was the origin of Phoenix, whose original business was writing non-IBM-copyrighted bioses for clones. Before that was done IBM forced many clone manufacturers out of business with licensing demands.

We did a board for a customer with a similar setup to the PC cards - SDRAM hooked to an FPGA along with PCI, a lot of NAND flash and some batteries. Data is normally stored to the SDRAM, when power fail is detected the FPGA automatically dumps the data into NAND flash and manages the bad sector mapping and error correction codes. The batteries are sized to sustain operation until the save is complete. On power up the data is restored and various flags and error status are forwarded back to the host CPU.

If anyone is interested e-mail me and I'll see if we have the rights to re-sell that design or can license it from the original customer.

Search for 'linuxbios' is an opensource project that has 100% sources for many mobo...

Alternatively, if you are building your board, you can use these as a starting point to develop your own bios....

goodluck

James