The Atmel application note about using the TWI (AVR315 dated 09/04) states that the TWBR should be set to a minimum of 10 and the prescalar should always be set to zero; thus disabling the prescalar. However the data sheet for the mega2561 does not mention either of these restrictions. Has the TWI changed since the issue of the application note or is it simply an omission in the data sheet.
I can think of at least one good reason for requiring at least 10 CPU clocks for each cycle of SCL, which is interrupt latency. Does anyone else have any ideas?