No, it takes 9 with a few adds and at least one subtraction. I forget the details, but it is in Knuth. It involves a suitable factoring of (a + b) * (c + d).
--
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
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Well, I can run our RTOS with all the services it provides on LPC210x, but I can't do that on PIC or even HC12 (we only support non-banked memory for now and it seems there's little or no reason to change that). Also, I like writing software for a decent 32-bit chip with "lots" of memory much better than working with limited 8-bit chips and optimizing the code using assembly language.
The input transients are the reason why we _need_ to be able to read the pin state. If we set the compare logic to detect a rising OR a falling edge and then have an input glitch shorter than our interrupt latency time, we will no longer know what the actual pin state is and we may program the compare logic to wait for the wrong edge. On Motorola chips, we always get an interrupt on both edges and then check for the pin state. If there was a glitch, shorter than our interrupt latency, we will see the pin is still in the "old" state and simply ignore the irq. If we can't poll the input state, we don't know whether this was a "real" edge or a glitch we should ignore.
Yes, it seems the pin is always an open drain output. :-I English is not my native language, so I may be misreading the datasheet, but to me it looks like the pin should be open drain in I²C mode only.
I think we know what is going on, now. If we try using the SS pin for GPIO, it might be that the SPI logic has the SS input pin (inside the chip) floating which causes SPI collisions. The Motorola engineers knew better - the SS pin was available as GPIO if it was needed for the SPI operation.
Do you know a contact at Philips? I'd like to get a confirmation for the things mentioned above. It seems we'll stop trying to use SPI and do it in software, so we don't have to modify the hardware (which is waiting to be delivered to a client).
And the PICs are _weird_. I hate them. And I still keep designing them into new projects. I am weird. :-)
-jm
Which one? AFAIK, ARM UMLAL et al. commands do make a 32x32 => 64. There are some severe register limitations, and shifting the result has to be done bitwise through carry. However, for fixed point fractional arithmetics the commands are just fine (rounding can be made with the accumulate part).
The AVR multiplication is 8x8 => 16, but yes, MSP430 may have
16x16 => 32, if that is what you meant.- Ville
-- Ville Voipio, Dr.Tech., M.Sc. (EE)
Karashiba (or something) algorithm? It should really work with nine multiplications, but IIRC it requires full 8-bit subtractions. This requires some work with the carry bit and absolute values, as otherwise some information is bound to disappear. Unless the processor handles this in hw, some manual branching is required..
With large multiplications the algorithm is far superior to the basic (elementary school) multiplication. If my memory serves, If my memory serves, its complexity goes as O(n^1.6) whereas the basic one is clearly O(n^2). However, with shortish numbers, the overhead may overtake the advange, again depending on the architecture. (No, I did not bother to write the code for any real processor, so this is just theoretical babbling :)
It may really be more economical on an AVR/PIC, but the difference is not very big.
- Ville
-- Ville Voipio, Dr.Tech., M.Sc. (EE)
Have you tried to buy any of the OKI parts? I checked the other day and found stock on several versions of both the ML67Q400x and the ML67Q500x. Try Nuhorizons and
Oh, UK. I don't know anything about how these parts are vended in the UK. But shouldn't Philips have a good distribution chain there?
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Does the ARM7TDMI have a 64 bit barrel shifter? If not, the slow part of a floating point operation is the normalization.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
No, my contacts are all in the US. I used to have a friend handling Philips, but they just pulled the line from the independant reps and now have an in-house sales force. I have a contact name here in Maryland, but I don't think that will help you much.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Only for addition and subtraction. The results of multiplication and division normally require at most 2 shifts to normalize.
--
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
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No, they don't have an FPU. (at least the ones I used) The advantage in doing standard 32-bit loating point calculations comes from the internal
32-bit egisters. The ARM DM versions also have 32x32 multiplies and the ability to do efficient shifts and rotates on 32-bit words. That all adds up to running software FP quite a bit faster than 8 or 16-bit processors---even those with hardware multiply instructions.Some VERY rough benchmarks I ran showed that an ARM 7 at 10Mhz had about twice the FP performance of a 68332 at 16Mhz. Of course, the ARM was running from internal 32-bit RAM and the 68332 used external
16-bit RAM.I would describe the MSP430 as more versatile, but the ARM7 as more powerful for complex data processing. That is particularly true if you want to work with more than 2KBytes of data at a time.
Mark Borgerson
I don't know if they'll really take off until there is a good Windows- based C compiler for under $500. Not all embedded engineers have the time to set up a Linux system and get a GNU toolchain running.
I would probably wouldn't have used either the ARM or MSP430 except that I had a customer foot the $4K bill for the IAR ARM compiler and I started investigating the MSP430 about the time ImageCraft came out with an MSP430 C compiler.
Now if ImageCraft will just do an ARM compiler---Richard are you listening? ;-)
Another possibility is to figure out how to use the ARM compiler in the MetroWerks PalmOS system to generate ARM code for an embedded ARM system. The PalmOS system is only $399, and it has been adapted for some 68K embedded systems. When I get some free time (yeah, right), perhaps I'll get the latest PalmOS system and see whether you have the ability to easily generate ARM binaries.
IMHO, a good LPC2104 demo board and fully capable C compiler for under $400 would sell like hotcakes in the Digi-Key catalog.
Mark Borgerson
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The GNU toolchain works prefectly well under Cygwin in a Windows environment. I built my first ARM7TDMI toolchain from GNU sources in Cygwin (in a NT4 computer).
The tools should also work with Mingw (minimal GNU for Windows). I have not tried it, however.
Tauno Voipio tauno voipio @ iki fi
Yes, but the lack of a barrel shifter is still more significant than the lack of a 32x32 multiply. Shifting by one bit is very time consuming. It is not relevant whether it is in the adds or the multiplies.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Yes, that is true. But there are few apps that need complex data processing, but not much ram. I am not saying there are not *any*, just not very many. In the same way, i would love to see an FPGA in a small package, like a 48 pin TQFP. But there are few apps for this sort of part and so they don't make them.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
No such thing. However, as long as the floating point is single precision fp, there is no real need for a 64-bit barrel shifter. Multiplications require very little shifting (two positions at max), so even the clumsy carry shifting works. Adding and subtracting requires more shifting, but still there is only 24 bits of data, so everything fits in the 32 bits.
With longer numbers the barrel shifter can be used piecewise, even though then a temporary register is required. The following pseudo- code shifts a double word (32+32=64 bits) r16:r15 by n bits using the barrel shifter
r0 = r15 shr (32 - n) r15 = r15 shl n r16 = r16 shl n r16 = r16 or r15
I guess it is more difficult to find out how much to shift (especially in subtractions which lose a lot of bits).
Of course, this is not as elegant as a real 64-bit barrel shifter, but bot very slow, either.
- Ville
-- Ville Voipio, Dr.Tech., M.Sc. (EE)
Ooops. The last row must be:
r16 = r16 or r0
Maybe it's now better.
- Ville
-- Ville Voipio, Dr.Tech., M.Sc. (EE)
One feature of i2c, is that (ideally) off devices should not clamp the BUS, so it may be that is a deliberate feature ?
-jg
In article , Mark
The Keil LPC2100 board is around 150 USD
/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/\ /\/\/ snipped-for-privacy@phaedsys.org
I do a lot of designs for scientific instruments where some data processing is done before storage, so I guess I see more need for floating point and large data arrays than does the guy designing the controller for a toaster oven. ;-)
I guess the FPGA would be nice, but I'm still working on
64-register CPLDs! One of those in a 44-pin QFP sure does beat a handful of LCX chips both in flexibility of design and ease of PCB layout and assembly. At my product quantities (100's per year), an extra 50 cents in part cost is less important that saving some design time, adding flexibility, and simplifying assembly.Mark Borgerson
I second this opinion. I do also design measurement instrument, and very often some rather complex analysis or calculations are required even though the data set is relatively small. Also, the bit banging requirements may be rather fast, which justifies the faster clock. In some applications multithreading is very useful, and doing that with a small 8-bit piece is usually not so simple.
Unless you are short of power. Some CPLDs (Xilinx CR2, Lattice Mach 4000Z) consume little power, but FPGAs tend to need a lot even at a low clock frequency. In this sense the modern MCUs behave better, their current consumption is almost proportional to the clock frequency.
- Ville
-- Ville Voipio, Dr.Tech., M.Sc. (EE)
Is a minimum of 5 to 10 mA (depending on temp range) low enough? The Altera ACEX (EP1K) parts are rated for this. If you are trying to get much below this, you are really looking at a speciallized application (or you can just cut off the power to the FPGA).
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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