ARM AMBA Designer licensing cost

A different department at my company handles the ARM licensing. I think we need to generate some AHB/AXI interconnect blocks, but in order to produce the synthesizeable RTL, we need an AMBA_Designer license. (We already have an SOC designer, ARM compiler/assembler environment.)

Due to some stupid politics, I'm trying to find out what it'd cost the company to acquire the necessary license to run AMBA_Designer, yearly maintenance. Then I can go to the project lead and beg, beg, beg. Is this a fixed price, or based on other ARM-IP we've already licensed (Cortex R4)?

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guestuser1
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You don't strictly need AMBA Designer to do that. The bus interconnects (PL300 or PL301 or whatever they have now) come with scripts to configure address ranges, etc. Writing the configuration file and the top-level signal plumbing is of course still a manual process.

Note that SoC Designer and I believe AMBA Designer, too, have been sold to Carbon Design. ARM has no business in these tools any more. At least not officially. Existing licensees might still be supplied with new licenses, though.

Like with every other EDA tool, everything is negotiable. I'd ask. End of quarter coming closer... Doesn't make any sense to quote list prices here.

Regards Marcus

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Reply to
Marcus Harnisch

Unfortunately, I need to generate a different interconnect (different # ports, AXI-to-AHB on one of them)

Really?!? Doesn't ARM Ltd still handle the RVDS package?

Ugh...if only my workplace didn't already hava a sales account. There's no way I could just call them up (using my company's name), without ARM asking me why I'm not the same contact who usually handles licensing...

Reply to
guestuser1

In message , guestuser1 writes

Yes they still have the ARM RVDS and the Keil-ARM compiler (almost the same beast) but they seem to have sold off all their other tools.

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Reply to
Chris H

Not quite. They still have the System Generator, which works similar to SoC Designer but operates at an even higher level. Code executes as JIT compiled native machine code and runs extremely fast. It is more a SW development than ESL tool.

Regards Marcus

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note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]
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Reply to
Marcus Harnisch

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