All of your parameters refer to the physical dimensions of the fet at silicon level, they are defined at the manufacturing process All of them refer to what they stand for, seen in a 3-D manner. Width = how wide is it Length = how long is it Depth = what's the thickness of the given layer Look at the parameters as a lying down rectangle with a specific thickness
None is affected by threshold voltage and gate voltage, in fact it's the other way around, the physical dimensions at silicon level affect these parameters.
None of them you can have any influence on, whatever you try, since it's a mechanical fact
I need some help in understanding the difference between -
Gate Length
Gate width
Channel Length
Channel Width
Channel Depth
Depletion Layer Width
Depeltion Layer length
for a MOS transistor. Which of these quantities are equal and how are they efected by threshold voltage and gate voltage. I am confused as to especially w.r.t depth and width.
Help is appreciated.
Kranthi.