IC manufacturing

IBM has recently announced a 2nm geometry.

Announcing and producing are two different things.

I believe this feature size has to do with the electrical channel and is not a physical feature. I'm wondering if the processing is truly continuing to advance with ever smaller features in proportion to this reference number? At some point the ever decreasing feature size will have to end since it is not practical to use X-rays in IC manufacturing. But then I'm not an IC designer, so maybe the will continue to come up with new tricks to make features ever smaller.

TSMC (soon to be in US AZ) produces the highest volume of 4nm for Intel's (unnamed) competitor.

As far as I know, you are completely right. The "2nm" or "1nm" is related to the geometrical feature that would have an "equivalent" conventional device producing the expected extrapolated performances (speed, power consumption, leakage or whatever...). Just for comparison, bear in mind that the silicon lattice constant is about 0.5nm, so the

The progress in manufacturing is mostly due to unconventional new structures (e.g. 3D fin fets) or brand new material or exhoteric semiconductor compounds. Indeed, a field of applied research that I am far for claiming trivial.

Classically the nodes were named by the minimum FET gate length. (You resize the device by changing the gate width, which is almost always much larger than the length.)

FinFETs started coming in at 32 nm iirc, in response to the creeping failure of Mead-Conway VLSI scaling. With VDD limited by gate length (a proxy for the width of the channel) and gate oxide thickness limited by leakage due to tunnelling, the only way to get enough E field to turn the FET on completely was to wrap the gate around three sides of the channel.

Since then processing has got hugely more complicated--instead of just silicon, oxygen, nitrogen, boron, phosphorus, aluminum, and copper, chips now contain most of the stable elements.

Ten years ago one of the major problems was huge variations in threshold voltage due to dopant atom statistics--it makes a lot of difference whether you have 90 or 100 dopant atoms in the channel, for instance. AIUI they solved that by atomic-layer deposition followed by local diffusion. Not your grandpa's quartz furnace anymore!

Cheers

Phil Hobbs

Phil Hobbs snipped-for-privacy@electrooptical.net wrote in news: snipped-for-privacy@electrooptical.net:

Burn baby, burn.

Whereas the silicon spike grown to produce the new kilogram standard was as pure and properly structured as it has ever gotten.

Moley, moley, moley.

Here's some videos on EUV machines by ASML:

1. The Extreme Physics Pushing Moore’s Law to the Next Level
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2. ASML: TSMC's Critical Supplier, Explained
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3. How ASML Builds a 0 Million EUV Machine
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Yeah, I did some work for them on that gizmo (not as much as JL though). The CO2 laser is impressive in person.

Cheers

Phil Hobbs

IBM has announced a 2nm process, and a new fet design:

IBM's 2nm transistors could supercharge your phone (in a few years)

IBM has produced a larger proportion of all silicon processing technology than any other organization. I haven't been there for a dozen years now, but I'm glad to see that that part of the IBM legacy continues.

Cheers

Phil Hobbs

There is a next-generation machine, somewhat more expensive.

I am more interested in the technology I can actually use for custom ASIC

Recently, the Efabless Google program allows for custom first try ASICs with no cost at all. Both free shuttle runs and free SW development tools

ASIC is no longer for big dollar firms ;-)

Cheers

Klaus