Hi all,
My friend told me if you want to get good timing, you have to make the ASIC with more area, is it right?
By the way, I have read a book(Advanced.ASIC.Chip.Synthesis), it said "For overly constrained design, DC tries to synthesize "Vertical logic" to meet the tight timing constraints.
Vertical logic:
***Is "Vertical logic" equal to more area and good timing?
Best regards, Davy
boki?
--
Thanks,
- Win
It depends on what kind of logic is in your critical path, but that is true in general. Usually, your slowest cells are the ones driving either long wires or multiple cells -- in order to make the faster, i.e. reduce their gate delay, you have to make their drivers larger, which increases the chip area.
Davy wrote:
hi Davy,
I want to give a simple example to understand the famous trade-off between area and speed, if we suppose that we want to do the operation : s= a.x+b.y+c.z
if we implement one multiplier and one adder we will need at least 3 clock cycles to calculate s, but the area is small. if we implement 3 multipliers and 3 adders the latency will be minimal (hardware operation) less than one clock cycle, but the area is bigest.
best regards Said HNAIN (Morocco)
Often, but not always.
< >^ | +---- This is your delay
Equal to? Not necessarily. There are several things that can be done to make timing. As has been pointed out already, one may do work in parallel so the slowest path is shorter or increase device size to improve delay.
One can also duplicate logic to reduce loading or wire length. Sometimes pipeline stages are added/modified to make the work fit the timing. Often buffers are inserted to reduce delays on long lines. ...lotsa knobs to turn to make timing.
-- Keith
Vertical logic is just logic that has lesser levels of logic at the expense of multiple gates. It looks vertical, i think, because of the way circuits are drawn. Logic at the same level are in vertical columns. Ex:
AND AND AND AND AND AND AND AND
is less "vertical" than:
AND AND AND AND AND AND AND
Not a good example in logic transformation terms but i guess the vertical part ought to be clear.
Aditya
Davy wrote:
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