That pretty much looks like John Fields' circuit, with one exception. For long-duration timers, there _must_ be a cap from pin 5 (control) to GND. Pin 5 is connected to the 2/3Vcc point of the three 5K resistors that are used as a voltage divider to set threshold and trigger values. The cap helps filter out power supply noise from messing up your timing. An 0.01uF cap is usually used here.
Also, you should have power supply bypass caps from pin 8 of each 555 to GND (0.1uF ceramics should work here), as well as having a bigger (100uF or more) cap on the board for filtering the power supply.
With those exceptions, if you do the layout right you should be able to get something that works for your +/-20% timing spec. As I said, it might be better to use a CMOS 555, and use the 1000uF low leakage caps and lower resistor values specified in the post above, but that shouldn't affect layout.
If you want better tolerance on the timing, you can compensate for the tolerance of the caps by tweaking resistor values up or down. But, like I said, John Fields' basic circuit will work.
You didn't mention what you're doing with the outputs here. If you're driving a non-resistive load, be careful. For relays, it might be better to drive them with an NPN transistor, and use a diode across the coil. And if the relays are driving an inductive load, use snubbers on the load or at least try to physically separate the relays as much as possible from the timer ICs.
If you're sourcing a lot of current (more than a couple of mA) from the output, you might want to consider using transistors and having the power wiring for the output wired separately from the power supply for the timer board.
Make your Vcc and GND traces as beefy as possible to minimize resistive voltage drops from point to point.
I'd be a little concerned about the load for these 555s. Please post again, and let us know what you're doing with the outputs.
Thanks Chris