are these diodes necessary?

That's an additional OR configuration if I understand your correction properly.

It's an additional logic function using diodes.

Graham

place -

properly.

Yes that's exactly what it is. So the diodes are necessary then?

Thanks

Of course.

Graham

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Giving it quick glance, the circuit makes no sense to me. Guess the inverters are open collector/drain types which require pull up resistors. Even then, the diode connected to the latch has been drawn in a wrong position.

petrus bitbyter

but you need a pull down resistor as well other wise with all four outputs at 0, the common point of the diodes will drift all over the place

Ok, thanks for all the help guys.

On Fri, 5 Jan 2007 16:17:06 +0100, "petrus bitbyter"

the op has clarified things a bit (top diode is on the wrong side of the common point of the other diodes) - if they ar OC, the iodes are not necessary, just a pull up resistor to give the function he is after

Thanks for your reply feebo. I guess I should clarify my question. If I apply a logic high using the 1st inverter, and there are no diodes on the other lines, 5v will hit the output of each of the other 3 inverters. Is that a problem, i.e., will the momintary 5v on the outputs damage the other inverters or affect their performance?

THanks

I think you need to specify what parts these actually are.

Graham

resistors.

the

other

Sorry - the inverters are a 4049 hex inverter, and the latch is a 74HCT373.

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Well, the CD4049 is a CMOS buffer/drover capable of sinking about 6mA and sourcing about 4mA (at room temperature and 5V power supply.) The 74HCT373 has a very high input impedance, mostly capacitive. Input currents can be almost neglected in this case.

So look what happens when you tie the outputs together. One output can be high, another can be low so you make a short between the plus and minus of your power supply. You may fry the inverters but even if you don't, the output becomes undedfined and useless.

Now look at the scene when you use the diodes as meant in the original post. (But moving the wrong placed one.) As long as at least one inverter output is high, the input of the latch will stay high. It is driven by the high output inverter via the diode. The low driven output(s) of the other inverter(s) will not short the high to ground as the current is blocked by the diodes.

So far so good but now look what happens when all inverters go low. The input of the latch is floating now, but nevertheless will stay high for some time. That's to say as long as the input capacity will keep it's charge. The latter will leak away slowly via the reverse current of the diodes. So eventually the input may become low. Nevertheless, the input will be undefined for too long a time to be usefull.

What you can do, is placing a pull down resistor of - let's say between 2k2 and 4k7 - between the latches input and ground. This way the input capacity will discharge fast enough to prevent the problems mentioned.

Next time you have a question give as much information as you have at once. It's crucial. When you were talking TTL circuits for instance I'd have to tell quite another story.

petrus bitbyter

Open collector outputs cannot "drive high" they can only "pull low" so you can link them all together and any one going low will take the junction low - because they can't drive high, you need a resistor to pull the junction up when no output is pulling low - this is a "wired and" function.

As you hav already stated 4049 inverters, these are not OC (or would be open drain in the parlance of the technology here). what you are doing is creating a "wired OR" where any high output will take the junction high. thus you need to provide a pull down resistor so that the junction actually goes low.

So to answer your question; As you are not using OC or OD devices, you do need the diodes. otherwise it is quite possible the outputs will destroy each other (or even the whole chip) as they switch state.

Well, I'm an old fart from TTL days, when the totem-pole outputs were a weak pullup to "high", which could be as low as 2.7V, and still qualify as a "high". So, when you parallel them, whichever output is "low" will actually overload the pullups on the ones that are trying to go "high". In other words, (at least with TTL) the effect will be the opposite of what you've speculated. (the ones going low will drag down the ones going high, much like in real life. ;-) )

This can be completely eliminated by using open-collector outputs; this is also called a "wired-or" or "wired-and" or "wired-nand" or some such - that way, the only thing that sources current into the "low" outputs is the pullup resistor.

Good Luck! Rich