Zetex FET driver low level?

• "Obviously" at no current (the gate in steady state draws no current). Values are not weird at all.

• Lemme ask: in a semi-ideal set-up, what kind of waveform would one expect using a single-ended driver (first,the NPN then the PNP)? The capacitor charges up from step time zero, meaning the voltage would drop/droop - so the "overshoot" then just might not be expected,but better the heck be seen...

Discrepancies? Only in your mind.

From experience on another component from them, you can use 2N3904 models for the NPN and 2N3906 for the PNP's Just pop into their topology and you get very close. Assume foundry is foundry, so may work for this component, too.

Exactly. And that's where I get very different values, the ones I expected.

--
Regards, Joerg 

http://www.analogconsultants.com/

When I do their test circuit i get close to what they are getting and I can see why..

They are not using a - rail in test setup, they're using 0 volts for the Vee. The cap has to get charged on the high side and it comes in short around .7 from the rail to start with, as expected, except for the initial corner pulse from the cap in the transistor.

Since you do not have a -Vee we are only discharging the cap and initial low side switch is going to introduce a high current peak which is coming from the cap in the PNP. This will cause the emitter to drop below a normal diode volt on the corner. At this point, there isn't enough charge in the cap to sustain a diode drop and looks lower than normal.

So in their test jig the high side is supplying a source where the low side is only discharging the cap with their simulated gate, which isn't much and results in lower than a diode drop reading

Looks normal to me, that's my take on it.

Jamie

So how did you make that overshoot happen? Run the ground wire over to your neighbor's yard and back? :-)

Cap in the PNP?

I can't see that happening. It also doesn't on the simulator. Easily fixable with a low-value resistor from base to emitter, I am just wondering how they came up with this weird datasheet stuff.

If you are discharging, say, 2000pF Cgs there is always a 0.7V pedestal with an emitter follower type buffer. It won't discharge any past that and if there is no other conductive path the gate charge just sits there.

Doesn't to me. Especially the start contrast between the left and right figure where only the load capacitance is different.

--
Regards, Joerg 

http://www.analogconsultants.com/

Storage can have that effect, dynamically saturating the emitter follower harder than it should go quiescently. At least, that's my guess.

Perhaps this is a time-domain hint at the effects that allow emitter followers to oscillate on capacitive loads?

This gate driver has such an output circuit (note the SOT-23 MOS driving the follower),

yet pulls curiously close to 0V: (2.2 ohm + 10nF load)

Tim

-- Seven Transistor Labs Electrical Engineering Consultation Website:

But not for such a long time.

I can see it being able to drift to zero, but not pull. Unless there is a pull-down resistor.

--
Regards, Joerg 

http://www.analogconsultants.com/

Once it gets there, where else is it going to go?

No pulldown.

So... my simple circuit cannot exist? :-)

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

Stuff happening on the output side (emitter) would pull it back. I have LC filters with ringing and all connected there.

Do you have a schematic?

I've never seen any such behavior in practice, emitter followers just won't pull to zero. Which is why I haven't ever used them to drive large FETs except with a low value resistor between the bases and collectors.

--
Regards, Joerg 

http://www.analogconsultants.com/

There's a thing called snubbing ;)

Not for that exactly. Nothing strange though. Imagine this,

but with an extra (discrete N/PMOS) CMOS inverter driving a beefier emitter follower pair.

Never had a problem; the emitter follower pulls hard to at least 0.7V, so as long as you aren't using logic level FETs, you're golden. And even that's not even bad if you keep R_G small.

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com

Generally not done in modern PWM. It can really spoil efficiency on high-speed scheme.

So how does the gate of the IRF510 go to zero point zero volts, even undershoot, and also overshoot +9V? That's what happens according to the datasheet but not according to my calcs, SPICE and the various circuits I have built.

And that's my whole point. Take another look at the IR datasheet. There it pulls to 0V and even dips below.

If you hang a low-ohms resistor from the collectors of the first pair in your circuit to the gate of the IRF510 the gate will pull much lower.

--
Regards, Joerg 

http://www.analogconsultants.com/