If the driving source is a voltage, current limited by a series resistor, maybe 50R, with controlled rise and fall times during the "0" gain portions, then the ESL and op-amps slew rate effects will be greatly reduced. Let's say 100KHz, 5V with 1.5uS rise and fall times. Now do your 1,0,-1,0 trick, add gain and filtering and feed to ADC. Sounds like a 800KHz osc divided by a flip flop to 400KHz and both FF outputs divided to 100KHz to get the driving and demodulating signals. Harry
Fred would be useful in a large R+D group just to keep everyone else on edge and razor sharp. He would not contribute anything directly but dithering the loop improves performance. If there comes a time when chaos insures then Fred must be controlled. I do that by filtering in the time frame and not replying to his rants. He on the other hand cannot control himself and will reply to this mild poke as a sock in the jaw. Harry
The HC405X switches like those voltages. Those who want to use a PIC may also want to include +4V and -1V so that the capacitor terminals that need to be near ground can be part way up on the ADC scale.
in
with
Hot air. Fraud.
John
He would have to be kept away from any design activity, as his attitude is poisonous to original thinking. He might make a good production-line test tech, where his rigidity would be an advantage.
John
in
with
Nya nya, nya nya nya nya! So take your marbles and go home. Who gives a f*ck?
...Jim Thompson
More like incoming inspection, where being anally retentive is a 'good thing'.
He has no marbles left to take home. It appears he lost them long ago.
Yeah, you're right. Test techs do need to be creative when problems come up.
My apologies to all the test techs of the world.
John
Sno-o-o-ort!
...Jim Thompson
Test tech sounds good but he is arguemenitive and the thru put would be zero. His effort and enthusiasm are outstanding but must be controlled. What if we inform him of the design requirements and let him research how this problem was solved in the past but never, never let him look at the on going design. I would still like him in the R+D group but he needs one of those Hannibal Lector face masks. Harry
in
with
That's in *your* world. I'm not concerned with it. Enjoy it. "Original thinker" my ass...
I'm sure it wasn't an intentional slur, John. :) Fred brings out the worst in a lot of people. OTOH, some engineers don't like test techs, because they find too many mistakes. Some rarely slip up, but others do it often enough to be tossed back out on the street. I only caught one mistake by the best EE I worked with. He was updating the divider board layout for a synthesizer, and was working from the original design folder. The original schematic didn't match the actual board, and some input pins on a ECL prescaler were inverted logic. That was one I hated to report. At least it was on the sample board to qualify the design, not a production run. One screwup in a little over three years isn't a bad record. :)
in
with
You don't like this?
How would you do it?
I like this little box, so I'm going to put a bunch of other instruments into it, too. A 4-channel arb is next.
Show us something you've designed.
John
The biggest problems I have with my techs is that they keep trying to fix things that are probably design errors, because they don't want to bother the engineers. We *need* to know that we messed up, so that we can fix it right.
John
A good technician is like a good secretary... indispensable.
I hired Jim Foster in 1964 out of a class I was teaching, and he stayed with me until 1990 when he retired.
...Jim Thompson
sunk in
really, with
troublemakers
Fred can't. He's the guy back there in the corner of the lab... you know which one, the guy with the broom ;-)
...Jim Thompson
When ESR is near 1-milliohm, step-driven ESL can take much longer than 2.5 or 5us to settle out.
The loop R is not 1mR but 50.001R. Let's say the worst case ESL is 1uH with 1.5uS rise and fall times, so the max dead time voltage spike is: E=1uH*5V/50R*1.5uS = 0.66mV. The time constant is, T = 1uH/50R = 20nS. Max Q = 6.28*100KHz*1uH/50R = 0.0125. The dead time will have small inductive components and the measuring intervals will have much less and easily summed out with sync detection. Harry
No, I think this doesn't help the ESL effects at all. With a high impedance source, the L/R time constant is shorter. With a 50R one the time constant is longer.
Why use an ADC? Whats on the far side of it? If you do much filtering before the ADC, you loose the advantage of the micro. If there is enough noise, the ADC's LSB get toggled by the noise and thus the quantization error is below the noise.
I would start with something like an 11.0592MHz crystal not 800KHz.
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