Do you mean page 25 in the real document? There ain't no page 29...
Anyhow, if yes: U2 controls the gate of Q1 so the voltage at the drain of Q1 equals twice the voltage at its pin 3 (on account of the divider R5/R6). Looks like the PIC spits out a PWM signal at CCP1 where the duty cycle is proportional to the voltage. R4 and C8 smooth that out to a nice DC level which then becomes the reference for the voltage regulator that U2/Q1 comprise. It's a low-dropout (LDO) regulator scheme, not exactly my favorite. This is also why pos/neg inputs appear reversed. They have to because a rising output voltage at the opamp actually reduces +V-TGT which probably is some kind of desired target voltage.
Hope this helps.