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VLSI question regarding parasitic-extracted layout

Hi, i'm not sure if this workgroups is suitable for VLSI questions but since this is the closest i managed to found so i'm going to post it here, hope you guys don't mind.

I'm working on a simple project of building a 6T SRAM cell. In the question, the a section of the report requires "Simulation results of the parasitic-extracted layout". Unfortunately, since my instructor is not around for a few days i have no one to ask so i was hoping if anyone here can explain to me what is it? And how do i obtain it?

I'm using the layout tool called MAGIC.

Thx guys....

Reply to
Ant_Magma
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I don't know how to do it, but your layout tool can EXTRACT a netlist from your layout that includes the parasitic capacitances (and sometimes metalization resistances).

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
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Reply to
Jim Thompson

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