Somebody wasn't being careful about where the spikes went. The sort of goof who dumps that kind of spike into a capacitor whose other end is buried in a board-wide ground plane deserves everything they get.
You do have to worry about routing switching spikes around the shortest possible circuit (minimal included area), and that does mean paying attention to every element around the loop.
I have seen the same SRD effect in discrete mosfets, in a half-bridge config where the lower fet substrate diode is conducting and gets hard reversed when the upper fet turns on. In that case, the spike blew out the gate on the lower fet.
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John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Too much deadtime, almost 20ns. Unforgivable in an IC that includes the MOSFET switches with well-understood delays. Also, sometime a little overlap is good.
The long dead time is maybe pumping carriers into the substrate diode, and encouraging it to snap.
The original SRD effect was discovered by Boff accidentally. Some PN diode just happened to have the right (or maybe wrong) diffusion profile to make it a step-recovery thing.
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John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Well, the trivial solution would be supply inductance. With a bit of damping, or a diode clamp, to absorb the reaction on the other half of the waveform.
Y'know, snubbers? Those old things? Yeah.
It's too bad that exactly zero percent of monolithic switching regulators are designed to do that. It would be great to have the switching transistor power separate from the logic power. But no.
I would imagine most regulators don't have enough PSRR to withstand a snubber spike* while operating normally.
*The spike is downward first (shoot-through pulls down on the supply), then upward (whatever was holding the node low (recovery, switching). It's a lot of high frequency voltage content.
With supply dI/dt snubbing, it's even reasonable -- recommended, even -- to push deadtime into the negative numbers (i.e., intentional shoot-through). Real efficiency gains to be had, in suitable situations. Nobody designs chips with adjustable deadtime though. Not a range like that.
The '3102's data sheet brags that it is an "Automotive Grade Product!", so I wonder if part of the issue was that they were mostly concerned with ensuring it could supply the (de-rated) max output current at 125 C rather than...other things...
The current shoot-through is from the top of the external bypass cap, into the chip (upper nfet turning on, lower nfet doing the charge-storage-snap thing) then out the ground pin of the chip back into the cap. After the snap, there is also the very fast voltage rise and ring at the output pin. So there are insane dI/dT and dV/dT at snap time.
How would you snub the current spike?
I have personally seen one synchronous switcher, and one discrete-mosfet switcher, that had the step-recovery effect. Most don't. I think it has to do with the diffusion profile in the substrate diode.
Snarkiness is not usually a successful design methodology.
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John Larkin Highland Technology, Inc
lunatic fringe electronics
We once built some 2KV, nanosecond-width, 100 KHz, water-cooled pulse generators, using drift step-recovery diodes. Nobody that I know of fabricates DSRDs on purpose, so one tests other devices hoping to find one with, accidentally, the right doping profile. Our favorite was the c-b junction of a high-voltage NPN power transistor.
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John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
It works fine if you have an external switch, but most integrated regulators don't have separate VCC (logic supply) and switch drain (or PMOS source) pins.
The charge stored in the substrate diode will be pretty much constant (spontaneous recombination is slow) so Vcc would be dragged down hard. Lots of nC.
Even with discrete fets, I'd sure prefer to eliminate the step-recovery spike, rather than adding an inductor and suffering the results.
That's sort of a new buck switcher topology, a synchronous half-bridge with inductors at both the input and output.
--
John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Yep. Recovery is slow, no matter how you cut it. MOSFETs necessarily make bad junction diodes (it's a doping thing).
The missing piece is adjustable dead time. If they provided this feature, it could be trimmed to 0 +/- 15 ns, say, rather than the usual overly-cautious and EMC-inducing 45 +/- 15 ns most chips have.
Supply inductance resolves the question of "how much current is drawn in shoot-through?". It's simply V = L * dI/dt, as with anything else done with inductors! No need for burning up transistors, it's just reactive energy. The energy can be "stirred" back into the supply, or burned in a resistor because it's not much.
A buck converter, operated in shoot-through, can have ZVS switching under all load conditions. Good for speed!
Depends on the switching frequency. If it is low, say 50Hz, the diodes can be extremely useful. For example, in my synchronous rectifier they trigger the rectification half-cycle. Here are some excerpts from my article (a cover story in one of Polish hobby magazines):
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It makes use not only of the parasitic diodes, but also of the parasitic gate capacitance, which greatly simplifies the circuit. The small toroids on the MOSFET legs are the place where the magic happens. For small currents the device is purely Graetz, for, say, >1A it is purely synchronous and in the transition zone it continuously morphs between these two states. It is very cool, for
Oh, and FYI, I once built a 400kHz industrial inverter (~5kW) that used the body diodes just fine. And that was with the old high voltage VDMOS, the kind with huge capacitance, terrible Rds(on) and ~800ns recovery time!
Obviously(?), this was only even remotely possible because it was a resonant ZVS application. The body diodes recovered acceptably by the time the channel was handling normal (drain-positive) current.
Not entirely sure of the behavior, but it certainly looks to have interesting feedback behavior. The IR21531S seems to be supplying a refresh clock, as it were, but that would imply it's constantly figeting, which would need a lot of inductance somewhere to absorb those events (perhaps the power transformer and TVS is enough?).
The feedback connection reminds me of the old BJT inverter circuits, that used load current to drive base current: the switching transistors were driven at constant-hFE, the ratio being defined by turns ratio between emitter and base windings. The controller actually forced the normally-on inverter 'off', by shorting out the drive transformer!
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