Transimpedance amplifier.

Hi,

I'm design a amplifier with a OPA657. When I would simulate the design with de model that you can find in

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I can not simulate a inversor with the orcad 9.2. The error is

ERROR -- Convergence problem in bias point calculation

Last node voltages tried were:

NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE

(N00634) 1.8848 (N00735) -1.8848 (N00885) -2.1145 (N00925)

-.0209

(N01022) 0.0000 (X_U2.10) 1.0518 (X_U2.11)

1.0700

(X_U2.12) 2.8169 (X_U2.14) 3.5962

(X_U2.15) 67.3720 (X_U2.17) -1.4889

(X_U2.18) 1.4889 (X_U2.19) -2.1570

(X_U2.20) -1.1148 (X_U2.22) .8426

(X_U2.23) 1.8848 (X_U2.40) 32.84E-18

These supply currents failed to converge:

I(X_U2.E_E32) = -10.00GA \\ -10.00GA I(X_U2.E_E31) = 10.00GA \\ 10.00GA

Try running with .OPTION STEPGMIN

What mean the error? Thaks

Reply to
jboix
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Post a SCHEMATIC showing how you connected it up.

Doesn't 67 VOLTS and 10GA catch your attention ?:-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

In message , dated Thu, 14 Sep 2006, Jim Thompson writes

He doesn't know that '10 GA' means 10000000000 amps. Quite a lot of people wouldn't.

Pretty good short-circuit, I'd say!

--
OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk
There are benefits from being irrational - just ask the square root of 2.
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK
Reply to
John Woodgate

Hi, I can wath that 10 GA is impossible but I can not understand why. I don't know as I can show the schematic in a picture and I copy the netlist of circuit.

  • source CUPRI_PROBA2 X_U1 N00155 0 N000036 N00111 N01425 OPA657 R_R1 N00155 N00111 1MEG V_V1 N000036 0 -5Vdc V_V2 N01425 0 5Vdc I_I1 N00155 0 DC 0Adc AC 1uAac

The model that is referenced OPA657 is

  • Schematics Subcircuit *
*------------------------------------------------------------------------
  • OPA657 Non-Unity Gain Stable, FET Voltage Limiting Amplifier
  • REV. A - Created 1/21/02 Rea Schmid
  • REV. B - Created 2/26/02 Rea Schmid - Purpose to adjust voltage and noise curves
* *
  • NOTES:
  • 1- This macromodel predicts well: DC, small-signal AC,
  • noise, and transient performance under a wide range
  • of conditions
  • 2- This macromodel does not predict well: distortion
  • (harmonic, intermod, diff. gain & phase, ...),
  • temperature effects, board parasitics, differences
  • between package styles, and process changes
*
  • |-------------------------------------------------------------|
  • | This macro model is being supplied as an aid to |
  • | circuit designs. While it reflects reasonably close |
  • | similarity to the actual device in terms of performance, |
  • | it is not suggested as a replacement for breadboarding. |
  • | Simulation should be used as a forerunner or a supplement |
  • | to traditional lab testing. |
  • | |
  • | Neither this library nor any part may be copied without |
  • | the express written consent of Texas Instruments Corp. |
  • |-------------------------------------------------------------|
*
  • CONNECTIONS:
  • Non-Inverting Input
  • | Inverting Input
  • | | Output
  • | | | Positive Supply
  • | | | | Negative Supply
  • | | | | |
  • | | | | |
  • | | | | |
.SUBCKT OPA657 + - Out V+ V- C_C4 V- 0 1P C_C2 0 V+ 1P D_D12 14 12 DX 1 V_V12 14 V- DC 4.54 R_R51 V- 23 9.0 R_R50 19 V+ 5 D_D51 Out 22 DX 1 D_D50 20 Out DX 1 D_D32 18 40 DX 1 D_D31 40 17 DX 1 R_R30 15 0 39.85K C_C10 10 11 950F E_E50 19 20 POLY(2) 0 40 V+ V- -765M 1 0.5 E_E51 22 23 POLY(2) 40 0 V+ V- -765M 1 0.5 J_J2 11 - 12 JX .5 E_E32 18 0 POLY(1) V- V+ 1.95 0.5 0 0 C_C6 Out 0 1P I_I12 12 V- DC 9.8M R_R10 10 V+ 750 R_R11 11 V+ 750 J_J1 10 + 12 JX .5 E_E31 17 0 POLY(1) V+ V- -1.95 0.5 0 0 G_G40 0 40 POLY(1) 15 0 0 1U 0 0 R_R40 40 0 1MEG G_G1 0 15 POLY(1) 11 10 0 245.84M 0 0 C_C30 0 15 8.55P C_C40 40 0 .195F
  • .model DX D(IS=1E-15)
  • .MODEL JX NJF(BETA=10.000E-3 LAMBDA=35.000E-6 IS=2.5000E-12
+ALPHA=1.0000E-6 VK=1 RD=1 RS=30 CGD=500.00E-15 CGS=100.00E-15 +KF=69.500E-18 BETATCE=-.5 VTOTC=-2.5000E-3)
  • .ENDS OPA657

Thanks.

Reply to
jboix

Make sure the node order for your voltage sources is...

V_V1 PosNode NegNode Value

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

  • CONNECTIONS:
  • Non-Inverting Input
  • | Inverting Input
  • | | Output
  • | | | Positive Supply
  • | | | | Negative Supply
  • | | | | |
  • | | | | |
  • | | | | |
.SUBCKT OPA657 + - Out V+ V-

Hello ,

Please compare the order of the pins in the subcircuit with your netlist and you will know what you have done wrong..

For a transimpedance amplifier, this line should be netlisted as shown below.

X_U1 0 N00155 N00111 N01425 N000036 OPA657

  • TRANSIMPEDANCE AMP X_U1 0 N00155 N00111 N01425 N000036 OPA657 R_R1 N00155 N00111 1MEG V_V1 N000036 0 -5Vdc V_V2 N01425 0 5Vdc I_I1 N00155 0 DC 0Adc AC 1uAac .END

Maybe you need an additional line to include the model if you work with on the netlist level.

.INC OPA657.mod

Best regards, Helmut

Reply to
Helmut Sennewald

Thanks, my simulate is running. Thanks.

Best regards, Juan

Helmut Sennewald wrote:

Reply to
jboix

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