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Transient Behavior of Coupling capacitors

When coupling capacitors are used to remove DC offsets between stages, does there exist a dc component during startup? I notice that when I watch the dc after a coupling cap that it starts out with a large dc component which goes to zero. I assume this is because the cap is charging and eventually charges to the dc component which blocks it resuling in a net 0 voltage after the cap?

Suppose I have an amplifier stage and I couple it to that of a jfet. In this case the gate is "floating". We could add a large resistance to ground it(lets say it requires a very large resistance to prevent loading... 10M or more). But will the gate initially have a large dc component which could potentially ruin the jfet?

e.g., I have a very high ouput impedence(~1M-10M) transducer with a high supply voltage(~1kV) and a relatively large DC offset(> 100V). I would like to create an amplifier.

I've tried a bjt but it simply loads the signal too much and I can't get the transistor out of cutoff without drawing too much current through the resistors(trying to use 1/4W or 1/2W). When I do load the signal/heat the bias resistors I can get some amplification(finally get out of cutoff) but the signal is distorted because of loading and probably because it is too close to cutoff.

Therefore I figured I could use a common source amp. Of course now I have to worry about blowing the gate. The signal switch is within spec but the dc offset would easily ruin it if it gets through the cap.

Anything I could do? It would be a relatively straightforward problem if the output impedance and voltages weren't so high. I would like to use basic techniques if possible rather than some exotic method.

If I could in some way buffer the signal then I can get away from the loading issues which is really the only problem I'm having.

Obviously some floating gate method would work but the only thing I can think of is a transformer and I'm not willing to go there.

Reply to
George Jefferson
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I should be a bit more clear(sorry, been up all night)...

The problem is that the previous stage has high output impedance and all the amplifier configurations requires some type of biasing. If the biasing resistors are to form a stiff voltage divider to prevent loading then they must be much larger than the output impedance of the previous stage. This requires them to be on the order of about 100M to 10G depending on the amp configuration. While I suppose this might work for some mosfets(such as the common drain) it doesn't work with any bjt's. I'm not sure I have any resistors above 10M to even test it and I imagine it would cause other problems?

Reply to
George Jefferson

Yes, that's basic cap behavior -- when the input voltage steps up, the voltage across the cap does not change instantly (otherwise it wouldn't be a cap), so the output voltage step up, then decays down.

If the source can drive enough current, yes. You can flow some current into a JFET gate without damage (as long as you have enough resistance on the drain), so you could protect the JFET gate with a series resistor, or some clever combination of series resistors and shunt diodes.

If it's really truly 1M, and not effectively 1M, then a 100V offset would only cause 100uA to flow -- that's not going to harm the JFET. OTOH, if it's some nonlinear thing that'll flow TONS of current at first, then you may have a problem.

Remember that you're not going to put any more charge into the JFET gate than will build up on the cap, so a smaller cap will help to some extent. A small cap in conjunction with a careful voltage ramp to the transducer supply will help more.

There are ways to get high input impedances from BJT stages. The easiest from a circuit designer's point of view is probably to find an off-the-shelf op-amp that'll do what you want.

What you're talking about building _is_ a buffer.

A transformer to work with a 1M-ohm source would be absurd. You're on the right track with a JFET, although if you can make it work with an op-amp you should seriously consider that approach.

--

Tim Wescott
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Reply to
Tim Wescott

Ok, I guess I have to ask the question different... I'll do another post.

ok, this is becauset he JFET's gate is much much greater so we effectively have a voltage divider effect with the "gate voltage" basically being 0?

Basically your making it sound like ultimately what really matters is not the absoltue maximim voltage but the current. If the max VGS is 100V and the internal gate resistanec is 1M, just for calc, then really we simply can't "force" more than 100uA into the gate?

Hence any transient voltage that may be much larger than 25V but doesn't put more than 100uA in the gate won't hurt it?

I'll ask in another post so you might respond to that.

Yes, I was thinking of using an op amp but I have read they can be bad in my situation because of distortion. Something having to do with all the extra bjt's in it that are not really needed.

Yes, but the problems of biasing still exist. Buffer or Amplifier(common drain/collector or source/emitter) still need to be biased which would cause problems. This is because the signal is AC

Yeah, your right... wouldn't be enough drive to get anything.

Thanks.

Reply to
George Jefferson

If I may butt in ...

If your output impedance is 1M and the voltage swing is 100v, then by Ohm's law, that results in 100 uA.

Now check your jFET's datasheet, and look for a spec called "maximum gate current". This is the maximum current that can pass through the forward-biased gate "diode" without causing harm to the device.

It will probably be several mA, so 100 uA is not going to hurt it.

However, another thing you'll see on the datasheet are maximum voltages for drain-gate and gate-source. Exceeding these will put the device into avalanche breakdown, and as far as any book or datasheet I've ever read on jFETs goes, this is considered a "no-no". jFETs are not intended for use in this region, and you are cautioned to avoid it.

No more than a discharge of static electricity would. ;-)

In other words, don't do that.

There are ways to limit the voltage at the gate of the jFET. Consider using back-to-back zeners or even some kind of TVS. But be careful about the capacitance they add.

If you can get the maximum voltages under what you read in the devcie's datasheet, and the gate current when forward biased under the maximum, and the total power dissipation under the max spec, then you should be ok.

Look around; there are very low distortion opamps! Much lower than what you get from a jFET, for sure. And you will still need to protect the inputs against over/under voltages.

Jay Ts

Reply to
Jay Ts

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