To maintain CMRR (common mode rejection ratio) of op amp

"two transistors are added to the input terminals of the op amp... whose emitters are connected" can you give a more thorough description of the circuit config or better yet an ASCII diagram

What is the high-side voltage? Does it vary? What are the power supply voltages for the op-amp?

I can't think of anything useful you can add to an op-amp to improve its CMRR in the way of a pair of transistors. Maybe the transistors are being used as Zeners to limit the input voltages?

You can use a matched pair of PNPs as a long-tailed pair to minimise the common-mode voltage, provided you have a suitable +ve supply to power the tail of the LTP.

But a PNP and an NPN . . . ?

Hi, thanks for u r reply

To simulate the effects of common mode input voltages, you need an OpAmp model that includes these effects... or roll your own:

Using an EVALUE behavioral element, create an output voltage that is (for example) 100K times the input differential voltage PLUS (again for example) ONE times the input common mode voltage [(VP + VN)/2]

That's RIGHT, ONE!

OpAmps are always specified as so many dB of CMRR, because, if they specified common mode GAIN, you would be appalled.

Be appalled ;-)

...Jim Thompson

One interesting feature of this circuit that suggests that it may not occur in the real world, is the choice of diode in D1 location.

Nobody in their right mind would apply a 120Amp schottky to establish bias in a low power sensing circuit, unless it was present and in use to do something else. If the latter is the case, it might be relevent to the disection of the circuit, as to proper function.

You need to show us connections to this diode and to the sensor and to the battery, without just resorting to VCC5 or VCC12 tags in the drawing.

The full nature of high current shunts can be pretty elusive, and physically hard to represent on paper accurately. Try harder.

RL

Your shunt currently has no reference to system ground, except through the sensor.

The correct way to insert common-mode interference would be simply to drive one end of the shunt with a ground-referenced signal.

Figure out what D1 is supposed to do, pick an accurate representation of this device and stick it in your model. The same goes with any other device in the bising network.

R4 and R5 dominate CM input network gain and sets the output to report with respect to the emitter jn.. R6 offsets this output by an EB drop. There is currently no reason for zero input to produce zero volts, as reported.

s.e.d. tries to discourage top-posting. Please respect this convention.

RL

this circuit doesnt make any sense to me either.

The choice of parts is very curious, the 4XXXXX is a very old RCA series, from circa 1970, I doubt if they're still in production.

The other transistor and diode are rather unusual parts too.

Also any attempt at improving CMMR is going to require all those resistors hanging on the op-amp inputs to be of very high precision and stability. For 60dB CMMR you'll need resistors of considerably better than 0.1% precision and stability. That's assuming the transistors do anything.

One way of improving CMMR *might* be to somehow pull down the voltages, precisely and exactly by the same amount. Unfortunately the circuit as-is has no way of measuring the original input voltages, so it can't subtract anything precisely.

A MUCH more sane way to improve CMMR would be to slave the op-amp's power supplies to follow the input signal. A pair of resistors and zeners would do the trick, assuming you have enough voltage headroom on the op-amp supplies, or you can tie their common side to the shunt bar.

That's where the long-tailed pair can come into its own, with most of the common-mode voltage supported across the transistors' c-e.

Say you have a tail resistor R, with bias voltage Vt across it and two matched collector resistors to ground of 2R, then you have a common-mode output voltage of Vt to deal with in a subsequent diff amp, which could be much less than the common-mode at the supply. Errors then reduce to transistor pair offset performance and mismatch between the two collector resistors as a function of Vt, not Vcm.

Unfortunately, I'm blocked from accessing the link to the circuit here at work, so I'm unable to add anything further in that respect.

Hi all, Great to recieve different ideas. In the ckt due to the unavailability of data sheets (transistors) i chose available transistors in the PSPICE, to run the simulation. Actually they are SMD(surface mounted devices) one is named as SC and another one LD. And the diode which is connected to Vcc (5V in this case) could be a ZENER diode. And op amp is a dual opamp named 513AI. The second op amp (which is not in the ckt) is sisilarly connected to the transistors but the diode is COMMON(its connecetd to the base of the transistor). Now i hope the things are bit clear.

Any way thanks and awaiting for suggestions................

RAF

Hi, after conneceting to groung ( the shunt ) with common mode voltage source the simulation is running. Initially i ran the simulation by removing the transistors and diode (R4 and R5 aswell) and resistor R6(200k) to ground making a simple differential op amp. By applying parametric simulation( different values to common mode voltage) with input voltage as 250mV. The output is with different curves with different values . Means common mode voltage effect at the output. Next i included the transistor circuit , resistors and ran same simulation, Now the output is different. All common mode voltages are separated from the output voltage and the amplitude between is alos reduced.

and reducing the offst output voltages.

How they are performing (trnasistors) means whats happening theoretically i am unable to understand. As u have suggested (Mr .Legg) up to some level i can understand. som more datailed expanation i am requesting u.

Your circuit uses a single supply for the op amp.

Any differential measurement that reports with respect to ground will suffer from the devices inability to produce outputs (and possibly receive inputs) that approach the 0V supply limit.

Reporting with respect to a diode drop above ground, providing this information is intelligable downstream, will improve linearity at the extremes of the circuit's compliance.

The output of your circuit is correctly taken between the Op amp output and the emitter node, not ground.

The accuracy of your model will depend on the model's ability to mimic real physical limitations in the op amp.

RL

Your circuit uses a single supply for the op amp.

Any differential measurement that reports with respect to ground will suffer from the devices inability to produce outputs (and possibly receive inputs) that approach the 0V supply limit.

Reporting with respect to a diode drop above ground, providing this information is intelligable downstream, will improve linearity at the extremes of the circuit's compliance.

The output of your circuit is correctly taken between the Op amp output and the emitter node, not ground.

The accuracy of your model will depend on the model's ability to mimic real physical limitations in the op amp.

RL

Hi Mr.Legg, I have gone through the material "single supply amplifiers" (rail-rail) from Texas instruments. In that it has clearly mentioned about input and output stages of the op amp. In the output stage the out put should swing between positive supply rail and ground ( for battery applications for example). Using BJTs the out put cannot swing complterly to the rails.For that two complementary transistors ( one PNP and NPN) are used . As u said the two resistors (r4 and r5) overtake common mode gain and sets the output to report w.r.t emitter junction. And u mentioned to take output between emitter junction and output resistor.

I have tried using PSPICE by taking the outputs as u mentioned. I am sending theoutput link here. The input i applied 250 mV ac with dc common mode voltage rane from 1-100 with 10 V increment.

The pictures are nice, but have little meaning without carefull labeling.

Just examining the schematic and assuming that the biasing network is successfull in establishing an output reference that is within a diode drop of the 5V supply, you can expect your circuit to function so long as the common mode voltage does not exceed the limits of

Vref x (15/5) - Vref negative. (the situation where the input pins approch the negative supply rail - in this case 0V)

.....if the input common mode range of your op amp model includes both supply rails.

If the emitter junction is the intended output reference, then R6 should also connect to it and not to the base of Q1. If you need to bias Q1, add an appropriate part that doesn't function in the gain network.

AH has mentioned this circuit's sensitivity to tolerance. You can model this by altering R1, R4, R3, or R5 by a fracction of a percent. This error is amplified by R6, R2, the same as the differential signal.

RL