tiny inductor with every bypass cap?

Jun 21, 2008 67 Replies

The internal ADC of TI 28xx is crap. It has tremendously inacurate internal reference and high zero offset. With 12 bits available, the true accuracy is about 8 bits unless you have the ADC calibrated.

There is no need for 4 layer board with 28xx. The layout can be done on two layers just fine. Been there, done that.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

formatting link

If you are not sensible about the layout, then God help you.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

formatting link

It is not a big deal to lay out the board for TMS28xx. Two layers work fine. With 28xx, the very important thing is the power sequensing on startup and shutdown.

Indeed. Especially as the power pins of the chip are supposed to be connected directly.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

formatting link

Yes. Bizarre is the right word. Two layers work fine for TI 20xx? No ground plane, no voltage supply lanes?

What about using one of TI's power ICs, with 3.3V 1.8V and Reset Generator?

T.I.

I feel, at times God helps me, and at times he works against me. Oh Well, I have to keep trying. In your previous post you said that 2 layers is good enough for TI 28xx. I did layout some low-speed microcontroller 2 layer boards in the past. Do you think a 100 MHz DSP board requires different skills. The board does not have much on it. The DSP, and a few other plain chips.

Thanks, T.I.

One of my colleagues in the ultrasound group at EMI was a rower with lots of muscle around the trunk - made him a lousy test subject for ultrasound imaging. I played field hockey, which mainly builds up the running muscles, and was much more transparent.

-- Bill Sloman, Nijmegen

they are also probably ferrite beads, rather than inductors per se. but I have corrected a few designs where the "engineers" really did use inductors. nasty little bobbin core things. yuk!

I've seen quite a few app notes with FBs liberally sprinkled everywhere. I presume this is because its easier than thinking. that being said, I have a design thats soon to undergo EMC testing where I have exactly followed the manufacturers recommendations for the FPGA & HY ships, but I plan on muntzing most of the FBs during a day at the EMC lab. odds on I can leave ALL of them off...

Cheers Terry

One design I looked at used a 600MHz agilent parallel/serial - serail/parallel chipset. there was a 1uH inductor between the 0V plane of the receiver/equaliser chip & the agilent serial/parallel chip 0V plane.

oddly enough the serial link seemed a bit flaky. that didnt stop the company from selling hundreds of millions of dollars worth of product, but it did meant they could daisy chain 2 units, rather than the dozens they planned on.

and there was no way I could convince their head of engineering this was a bad thing. OTOH they paid my bill, and I did fix a whole host of other problems.

Cheers Terry

It depends. Really nothing special is required for TMS28xx for the EMI and the signal integrity purposes. However if the board is supposed to sustain the BCI test, then you will have to use four layers or more.

Generator?

Don't know about the dual regulators, never used those. Check the sequensing specs very carefully; it could be the false states at the outputs at startup/powerdown.

Vladimir Vassilevsky DSP and Mixed Signal Consultant

formatting link

Yes. Switching power supply hash.

Guy Macon

Hello Vlad,

We were able to arrange for calibration of the ADC on board and could easily deal with the offset issues.

We went 4 layer because we wanted it to work first time, 6M samples/sec and reasonable ADC performance for an on chip quite fast ADC.

It worked and was delivered on time and to spec.

Sure we could have got it on 2 layers, delivered it late, not quite working and saved a few £ on the board.

Did you never hear of "good, cheap, quick - pick any two" ?

Michael Kellett

Mad man Muntz must be spinning in his grave.

on

true

around

easily

and

working

We develop the consumer applications where every $ matters. Two vs four layer PCB is a big difference in the cost, so I don't use the multilayer boards unless it is really required. Despite of the popular beliefs, many analog or digital designs can be built in two layers just fine. It takes care, understanding and attention to details.

I averaged several sequential conversions of the 28xx ADC to get better noise performance, so I traded the speed for the SNR. It worked like expected for the noise however the problem was the beat tones between the ADC clock and the peripheral clock. Had to optimize the division ratios. The ADC manual is pretty vague (as it is usual with TI), so it is not clear what is the exact position of the sampling instants of the sequencer, and how the whole thing works. What set me off is that there are two similar but not quite the same sequencers there. Another stupid thing is that the ADC range is 0...3V absolute, not 0...3.3V ratiometric. So the 3.3V can't be used as the reference for the level shifting, etc. unless the 3.3V is measured against the internal reference.

Vladimir Vassilevsky DSP and Mixed Signal Consultant

formatting link

Much of the time that's probably so, but not always -- I know a guy who's a decent engineer, having run his own successful (profitable) company for awhile, working as a consultant, etc., before deciding to become an FAE once he got somewhat older and just wanted to settle down a bit and spend more time with his wife and kids. I can definitely see some of the attraction... you get to work on a much wider variety of projects than most regular engineers ever would, yet the stress level is probably much lower than those engineers who are facing tight deadlines and still have many unsolved problem. Indeed, a good FAE can really relieve a lot of that stress by providing real, working solutions to their needs.

Personally I'm suspect of anyone claiming to be an FAE who doesn't actually have access to (or chooses not to use) a workbench, test equipment, and whatever else they ought to have to be able to adequately build and test the circuits/ICs/whatever they're recommending. Unfortunately, this does seem to be a rather large percentage of all FAEs.

Hi Vladimar,

For many companies, coming up with that "care, understanding, and attention to detail" requires both significant time and often money -- so I think MK's point is valid, since those are not always available!

But I think that all of us would be interested to hear your advice on designing high-speed/low-noise circuitry on two-layer PCBs; it's not the sort of material that's commonly discussed.

Do you recommend any microcontrollers or DSPs with decent references on-board? We use a number of Atmel AVR microcontrollers and most often it's with an external reference, as the internal one is pretty bad; about +/-10% (!). Being charitable, I want to believe that you just can't build a reference that's much better using whatever process they have available to them, but perhaps it is just a lack of better circuit designers (e.g., someone like Jim could easily build them 1% references using the same process).

---Joel

Shhht! You are taking away a chunk of my source of income :-)

Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.

It never fails to impress clients when changes consist of lots of parts being replaced with a snippet of wire.

You had Muntz TV sets in NZ???

Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.

Classic question of the development cost vs production cost; it depends.

There is no magic to it; just understanding which way the current flows and distinguishing a ground and a signal return path.

Analog Devices ADUCxxxx series.

The good thing about AVR is that it is possible to use the external reference, and that the ADC input range is from 0 to Vcc. The ADC of TMS

28xx can't do that.

Perhaps there is a limitation of the high speed CMOS process which doesn't allow making reasonable on-chip ADCs. May be Jim can explain us why.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

formatting link

Thanks, I'll take a look; always interesting to see what else is out there.

What Atmel did poorly with the AVR was allowing for a second, low-speed oscillator for, e.g., "sleep" mode. They can do it, but only just barely -- they let you run one timer off of a second clock source (such as a 32kHz cystal), which then wakes up the CPU to do whatever. Workable, but nowhere near as robust as the TI MSP430, where some of them let you have a couple of clock sources (e.g., 32kHz and 16MHz or whatever), run the entire CPU off of either one (or the internal RC oscillator), switch between them on the fly, etc.

I'm told they've attempted to imprveo on this situation in their new "xMega" AVRs.

---Joel

nope, I just read widely. and this design absolutely had to work first time, so I just corrected the obvious errors, and planned the muntzing for a 2nd spin cost-down :)

oh yeah, I too know the evil twisted wire trick.

Cheers Terry

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required