T PHL and T PLH: why can they be different?

Did you read anything about how the circuits work? Look for asymmetries in the device properties and circuit topology.

Hint: the physics of PMOS and NMOS devices are not as similar as they might seem.

Cheers

Phil Hobbs

Thanks!

Generally, because bipolar transistors aren't symmetrical, top to bottom.

These days, with CMOS, that difference is being eroded.

Hope This Helps! Rich

I think it has more to do with circuit design, actually, in bipolar ICs. Look at 100k ECL for a counterexample.

Physically, the different mobility of p and n carriers means PMOS and NMOS transistors can't simultaneously be matched for conductance and capacitance, in Si. CMOS isn't as symmetric as ECL.

Your forgetting the output emitter follower. It's hardly symmetrical.

Bipolars are asymmetrical because lateral PNPs suck (so no PNPs).

A lot closer than PNPs can be matched to NPNs (in a monolithic process).

ECL isn't symmetric because of the output difference.

te:

Hah! 100k ECL is differential. You kind of walked into that...

The relatively small logic margin of ECL means the outputs are mainly the same impedance whether high or low.

You got a link to a schematic?

te:

l.

Try this one...

I think it was a family originally from Motorola, MC100xxx part numbers. The current suppliers include ON and Micrel. DigiKey has these in stock...

I don't see a schematic.

te:

ical.

No, the data sheet lacks a schematic. It's a sign of the times. All ECL inputs are basically differential, and the fully-differential outputs are just two standard ECL output circuits. So, the manufacturer's data doesn't show anything but the block diagram. The 'reference generator' that satisfied the second input to the ECL input pair of 10k ECL just isn't provided in the 100k series chips.

The data sheet DOES illustrate the point about rise and fall times matching, though; it explicitly specifies the "rise/fall" time as one value.

I really need a schematic to see the big picture.

Datasheets are known to lie.

te:

NO, you need to stop asking for a schematic and THINK. It's a differential logic scheme; high-to-low transition is done by one output going down, the other going up. And low-to-high is done by one output going down, the other going up. It's the same operation either way, just swap the pin numbers next to the description of the transition.

Don't get hung up jonesing to see a schematic; it's trivial to get an ECL AND gate and make its inputs and outputs differential. The magic is in the differential nature, not in the transistor by transistor implementation detail.

Don't be ridiculous.

I want to *SEE* the differential output topology, dummy!

Don't be so stupid.

Something like this?

Cheers! Rich

Nah, that's the classical (MECL-2, MST-1, or before) current-switch emitter-follower topology. I want to see the symmetrical output stage Whit is talking about.