stretching a pulse

It's an ideal circuit, and ideal integrators don't drift.

In real life, the signal chain would be easier if it were AC coupled, so we can just hang a simple DC restore circuit after the integrator. Detail.

The shorted-line thing is looking better, actually

input----50r-----+-------integrator----out | | | | | 50r transmission | line | | gnd

The ideal transfer function is perfect: impulse in, rectangular pulse out. And it uses the delay line twice.

We've got some samples coming of a 3 ns MLCC SIP delay line that looks to be pretty good. It simulates beautifully, of course, making a 6 ns flat-top pulse.

John

And light doesn't get any blacker than black, so our photodiode only makes positive pulses. We can DC restore just before our comparators.

John

Here's my ultimate burst frequency counter, all inside an FPGA.

ftp://jjlarkin.lmi.net/Burst_Freq.JPG

We know when the LC oscillator is running, so within its burst we generate a gate pulse.

The gate enables counters to count the rising edges of the 50 MHz LC oscillator and a separate 100 MHZ (or whatever) XO. We'll accumulate counts of both until we have enough for decent statistics, a million counts or so, and divide to get the LC frequency.

The trick is that the gate generator logic must use a third oscillator that is uncorrelated to the things being measured. It jitters one F3 clock period relative to, well, anything else. This board will have a bunch of XOs for the FPGA, the uP, the Ethernet phy, so that's easy.

Because the d-flop edge catchers might have some picoseconds of asymmetry in their D response, we'll use muxes to swap the flops on alternate shots, to even things out.

No, those aren't real delay lines, they are some simple clocked logic things to make the flops look like one-shots.

John

So

ding

Actually, I'd put grounded fingers between the zigs and the zags to deal with the sideways coupling - my 16 thou notional example included just such a grounded trace.

Sure. But you want to tap it from time to time, and the taps want to be reasonably close together. I'd buffer the taps myself, and narrow the delay trace around each tap to compensate for the capacitative load presented by the op amp input.

Printed circuits are components very like any other. You need to know how to calculate transmission line properties, but if you stick between 50R aand 75R this isn't usually too difficult.

-- Bill Sloman, Nijmegen

But you only have to keep about 1000 samples to feed to the analyser, and trigger the analyser instead of the sampler.

Digitizing and analyzing a signal like this makes no sense. All I want to do is drive a few comparators, and it's easier if I can use cheap CMOS parts instead of expensive power-hogging ECL ones. So, the quest for a pulse stretcher. Even if I did want to digitize the photodiode pulses (which concept was rejected by the customer on account of cost) it makes sense to stretch them first. Then I could get by with a 500 or even 200 MHz digitizer, which is beginning to seem sane.

John

Wilkinsons have perfect differential linearity but are very slow. If I did an analog peak-hold circuit and a 10-bit Wilkinson conversion in, say, 250 ns, the clock would have to be 4 GHz, which I can't do in an FPGA.

A 6-8 ns pulse stretcher and a 20 MHz ADC makes more sense, but is still probably a bit too expensive for this application. But I still would need the stretcher.

John

Are you measuring the peak power or total energy? If the latter, why can't the pulses simply be integrated by some fast analog front end, and the resulting integral sampled? Then reset the integrator in the "leisure time?"

We get a photodiode pulse, a spikey thing about 2 ns FWHM, and want to measure the peak. The original light pulse is picoseconds, so we're just seeing the impulse response of the photodiode. Given that, we may as well slow it down some more, to make it easier to process. I suppose the pulse height is proportional to laser pulse energy.

The stretchey thing sounds simpler to me than integrate-and-dump. It's sort of self-timing.

John

We get a photodiode pulse, a spikey thing about 2 ns FWHM, and want to measure the peak. The original light pulse is picoseconds, so we're just seeing the impulse response of the photodiode. Given that, we may as well slow it down some more, to make it easier to process. I suppose the pulse height is proportional to laser pulse energy.

The stretchey thing sounds simpler to me than integrate-and-dump. It's sort of self-timing.

John

I have a rescued video card here where the layout has some delay lines or loops marked 5mils/60ohm, and L1, L2, L3, L4 marked for two of these patterns, one each side of the board, apparently with ground plane between them. In case it stirs the imagination, I put photos up here, against a metric ruler:

I have no idea what it means, just another thing I wondered about.

Grant.

That's probably an impedance test coupon. People sometimes put them on boards and make the PCB houses match the impedance to some tolerance.

We often put test traces on our boards, zigzagging through various layers, to see if we (and the board houses) did things right.

The J28...J29 path does that here:

ftp://jjlarkin.lmi.net/Z250A.jpg

ftp://jjlarkin.lmi.net/Z250_TDR.jpg

John

Buh-b-but... you want ten bits? For that, why would you consider using a lumped-constant delay line, something like a few-poles approximation to a real delay line, with uncertain stability of attenuation and impedance? Those packaged 'delay line' gizmos, in my experience, are for digital timing use only, I'd expect about four to six bits of compliance to the idealized model of a delay line.

cascading

Good plan. I'm trying to convince them to do that on our boards, at least in the kerf area. We got burned by one board house and I'd like to prevent a similar occurrence. The problem is that we have to get the nominal resistance up well above 2ohms so ICT can measure it. Or maybe make it just under and do a go/no-go test.

AC performance isn't an issue. They screwed up the trace resistance and couldn't explain it away, except that apparently physics is different in their hemisphere.

cascading

Most board houses, nowadays, start with very thin copper, 1/2 or 1/4 oz, and then plate up. And they tend to skimp on plating. 1 oz copper should be about 550 uohms per square. I sometimes add a resistance test trace, and I seldom get the copper thickness that I call out on the fab drawing. If conductivity matters, like for high current stuff, you've got to tell the board house that you are serious about it.

John

So

cascading

AIUI, they start with 1/2oz and plate from there on the outer surfaces, while the inner planes are what they are, as the final plating is done after lamination. It's not that the conductivity mattered so much, as that they couldn't give us an honest answer to the question of why they were 2x nominal. That is, their plating was correct, the trace width was correct, and there was no contamination of the copper, but the trace resistance was 1.5x to 1.9x. They said they may have some pin-holes in the copper. ...more like foam. If any dimension was off it wouldn't have been so worrisome, but any necking or "pin holes" that would cause that sort of difference is. That they couldn't give us a straight answer was the reason they were dropped as a supplier. ...so we went to China, instead. :-(

We could, but that would be another inspection test. I was looking for something that could do 100% inspection, free. Our ICT's open/shorts threshold is 2ohms. A 25", 6mil, trace on 1oz. copper is about 2 ohms. We have one such trace on our main board and they were coming in at about

Fair enough.

Cool part, 3 ns MLCC sip delay line:

ftp://jjlarkin.lmi.net/Elmec_3n_sip.jpg

This is a tdr/tdt sampling scope pic. Bright trace is input, dim trace is output. There's an extra ns or so of cable delay.

It's an Elmec FDC3005A. They make surface mount, too.

We can use this in the shorted line + integrator config to shape an impulse into a 6 ns rectangular pulse.

John

This looks practical, no integrator required:

ftp://jjlarkin.lmi.net/Stretch_5p_Bessel.jpg

The delay line might be a stripline pcb trace, or one of the packaged ceramic things.

John