Strange high frequency push pull transformer action

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Betcha he finds this:

.-------------> | .---> | | '-'-'-'-'-' ============= (A) .-.-.-.-.-.-. (B) | | | +5v-' ||--' '--|| |||| Q2 __||--+ Q1 +--||__ | | === ===

That would explain the first waveforms, anyhow.

Not always: One of the guys in our army unit was building a hobby electronics project. He sat at the desk in his socks. Something unsoldered itself, fell down, melted through a sock, lodged itself between his toes ... phsssss ...

Shot in the dark:

It could be miller effect due to the capacitance between the drain and gate.. The opposite side is generating a pulse in an instance and thus the cap located there is pushing a pulse over to the gate and forces it to bias on. Of course this is short and shouldn't last long however, at the frequency you are operating at, it maybe showing the effects if you are not driving the gate low and hard enough in the off state.

You should probe at the gate of Q1 when Q2 turns on.

Jamie

My bet would be this (asterisk is winding orientation dot):

.-------------> | .---> |* | '-'-'-'-'-' ============= (A) .-.-.-.-.-.-. (B) |* | *| | | | ||--' +5v '--|| |||| Q2 __||--+ Q1 +--||__ | | === ===

mary

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Could be of course, but Vds(Q2) would go to zero when Q1 was on, not

That is strongly my suspicion as well. Just catching hell trying to prove it to the transformer designer/vender.

And the "baseline" would go up to some flyback voltage, probably with an exponential L/R decay, not just +5.

The asymmetrical waveform makes sense for the unbal (one driving CT) case, but only on the middle transistor. A dual trace scope shot, monitoring both drains, would be illuminating.

Tim

I considered that as well but the miller cap with a falling drain voltage would turn off the Fet not turn it on.

Gate drive resistance is a bit high at 200 ohms so I considered that as well. Driver output resistance is in the 10 ohm range

Still poking around. You guys thoughts and responses are great and confirming that I'm not crazy. :)

The transformer guy is saying it is some fancy RF stuff and I don't have the background to say he's wrong but my gut says its something 1st order that is the problem.

Nope, Tested for that and when Q1 would turn on Q2 would go negative ( at least until the body diode turned on. Then all hell would break loos on Q1s current.

That was my first thought as well. Ready to swing my big hammer and see if that fixes it. :X

I a haven't had much time in the lab to poke around with it. its "kinda" working as it is (good communication) but the SNR is much lower and I was after. This has the priority lower than it should be.

I still think it's miller effects, only because of the voltage you have indicated, which is ~ 2.5 volts, and the Vgs(th) is around 1.5 or so for a 700x and putting that in context the way it is, it's making a nice clamp at said gate voltage minus a little due to R(on). The fast raise from the opposite side is forcing this condition.

Putting a much slower signal in there as a test could verify that and you could then watch the.

Oh well, what a world!>..

Jamie

Not really. Those 2N7002 have several ohms Rdson, then there is the wire resistance in the transformer, all sprinkled with a pinch of leakage inductance.

I had considered that except the OP said, "If I probe Q1 drain instead of Q2, I get the same result. where Q1 goes from Vin to ground and goes from Vin to ~ 1/2Vin when Q2 turns on."

Which implies there isn't a circuit asymmetry.

Needs cold filtering?

Best regards, Spehro Pefhany

-- "it's the network..." "The Journey is the reward" snipped-for-privacy@interlog.com Info for manufacturers:

True, but none of that should matter, right? The Q2 winding section is supposed to be unloaded when Q1 turns on. Essentially no current flows in Q2, so the Vd(Q2) should match Vd(Q1) nearly exactly.

mary

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Agreed, it just didn't seem that all these statements can be true, so I took the most likely guess.

Would you rather pass it through a team of Clydesdales? ;-)

Probably taste better!

Tim

On a sunny day (Mon, 05 Nov 2012 21:17:17 +0000) it happened Mike Perkins wrote in :

I thought last night that perhaps he made a layout error and one FET is in the wrong way. Something like this pad configuration: 0 0

would NOT work :-)