Is there a canonical topology to stack them in series such that one gets a switch with a higher Vds rating but maintain approximately the same switching speed?
- posted
4 years ago
Is there a canonical topology to stack them in series such that one gets a switch with a higher Vds rating but maintain approximately the same switching speed?
Yes, each one needs its own {isolated} high-speed high- current gate driver. Usually some effort is put into matching the gate-driver delays, but MOSFETs don't mind avalanche breakdown and are tolerant of using this to protect themselves for a short time. But since you're talking about speed, one danger involves dealing with the voltages developed from high dI/dt.
-- Thanks, - Win
Win is right, but you might also consider silicon carbide fets. How much total voltage do you need? Can the switch sink to ground? How fast? How often?
Sometimes one can arrange to drive only the lower, grounded-source fet in a string.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement
I vaguely remember a circuit in AoE3 like that... with resistors and /or zeners to turn on the other gates? But not as fast I'd guess.
George H.
Figure 9.111, pg.697 GH
I was mostly hoping for an expedient, temporary solution as I need to test a circuit that requires 100 volt-rated FETs but I only got 50-volts in stock and I'm waiting on a shipment, and I'm impatient. the drive frequency is only about 1 MHz switching under an amp.
In this case that might be an option to get on with business for a while.
Isolated high-voltage drivers require special circuits, usually involving transformer-powered circuit fragments. But at voltages below 600V, you can use high-side driver ICs, like Fig 3x.108, Table 3x.5. Drive sets of stacked MOSFETs. Probably none of those in stock either, huh?
-- Thanks, - Win
Sigh....
Try two series FETs, with the high-side FET shorted gate-source. Then drive the low-side FET. The high-side will avalanche when it sees the full 100V. Will this work? I doubt it. But at a glance I can't see why not...
If the duty cycle is reasonably far from 1 and bipolar drive is not a problem: Ze Transformah...
Best regards, Piotr
If the duty cycle is reasonably far from 1 and bipolar drive is not a problem: Ze Transformah...
Best regards, Piotr
Low voltage NMOS and high voltage SiC JFET in cascode configuration?
-- Cheers Clive
The OFF condition should be OK. But for the ON condition the high-side FET will remain off, except it may avalanche at some voltage. At any rate, the output won't be pulled down to GND.
-- Thanks, - Win
That circuit looks good. Nice find!
The secret is the gate capacitors to GND, with zener protection diodes for the FETs Vgs. If there's no load for pullup, a high-side switch will also be required. But it's not clear why the high-side switch can't use the same trick as the low side, employing only one isolated gate drive on the bottom FET of the stack.
-- Thanks, - Win
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Look at AoE3 figure 9.111, Maybe Paul put this one in there?
GH.
No, I put that one in there, but I'm not sure they'll work the same. Our caps were meant to help equalize Vds drops, whereas the paper's circuit, with a separate cap to ground for each MOSFET's gate, insures that it'll be aggressively turned on if its source is pulled down. Anyway, it's a quick easy circuit, nicely satisfying the O.P.'s request.
-- Thanks, - Win
A brute-force way to do this is to use some commercial (or home-made) gate driver circuits and float them on each of the fet sources, with dc/dc converters to power each one. DC/DC bricks with high isolation and low capacitance are cheap nowadays. Get the signals up there through an IC isolator or a small transmission-line transformer. Works for high and low sides.
-- John Larkin Highland Technology, Inc The cork popped merrily, and Lord Peter rose to his feet.
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