Spice Modeling Resistors with Distributed Capacitance

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Good find on the Vishay site:

They mention Modelithics. FL and their web site has an Whitepaper on Modeling RL&C's (presumably for RF) I found it here:

Good luck Cheers

Seems to me that all you need to do is break the line up into RC sections that have time constants considerably below 10 ns. A factor of 50 or 100 maybe, like 2*pi and then another order of magnitude or so.

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Thanks, Martin! ...Jim Thompson

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sum of time constants?

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Well, if it is physically simple, like rod-shaped with metal end-caps, naturally c-to-gnd on ends is larger than anywhere else in the middle-to-gnd. Maybe use half of the sum of those two at a point along the resistor body at a distance equal to the diameter of that endcaps.

[[[---------------------]]] | | | | | | | | | C1 C2 Cm Cm Cm Cm Cm C2 C1 where C2=0.5*(C1+Cm) | | | | | | | | | - - - - - - - - - (gnd)

And use at least 5 segments in the "middle".

Naturally, you do a similar trip for capacitance from one segment to the next.

I think that's right, assuming that there's some reason to believe that the capacitances are all the same, e.g. in lossy microstrip. With a SMT resistor, I doubt that's the case, owing to the short & tall aspect ratio and the presence of the end caps.

Cheers

Phil Hobbs

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rote

T

How much range of capacitance caused by variation in mounting height? ...assuming a GND plane, and not a cutout, under it?

Looks like a good time to estimate using femm, or calculate using Ansys HFSS, or better yet - measurement!

Major problem in measuring: added capacitance!