Spice Modeling a Typical Wall Outlet

When you actually have to make these measurements to test for regulatory compliance, you will usually use a LISN

Thanks..

I googled LISN.. I'm doing some reading on:

that

on:

look for an earlier s.e.d thread on building your own LISN Paul Mathews

You might want to consider the nature of the voltage source (upstream of the utility company transformer) as well. This will be a 60 Hz sine wave plus a whole gob of odd order harmonics. I'm not sure what your local power quality limits are, or what sort of testing requirements you have to meet.

that

If I got this right...

The typical FCC LISN schematic for smps supplies is:

LineDUT | | 0.1uF | +--------+ | | 50 ohm FFT | | Earth GndDUT | | 50ohm FFT | | +--------+ | 0.1uF | | NeutralDUT

I'm doing the FFT in LTspice. This is a spice project just to educate myself in smps design. I guess all I need to do is Google up the FCC spectral limits for conducted noise. D from BC

that

oops...I think there's a 50 ohm termination at the FFT...so..

LineDUT | | 0.1uF | +--------+ | | 50 ohm FFT (50ohm terminated) | | Earth GndDUT | | 50ohm FFT (50ohm terminated) | | +--------+ | 0.1uF | | NeutralDUT

D from BC

that

clipped from web:

Section 15.107 Conducted limits.

Frequency of ---- Conducted Limit ------ Emission (MHz) QPeak Average ------------- ------------------- ------------------- 0.15-0.5 66 dBuV to 56 dBuV* 56 dBuV to 46 dBuV* (2000 uV to 631 uV*) (631 uV to 200 uV*) ------------- ------------------- ------------------- 0.5-5 56 dBuV (631 uV) 46 dBuV (200 uV) ------------- ------------------- ------------------- 5-30 60 dBuV (1000 uV) 50 dBuV (316 uV) ------------- ------------------- ------------------- * Decreases with the logarithm of the frequency.

Qpeak??...what's that? Average?? That seems a bit foggy. Decreases with logarithm of f... I need a graph :(

Maybe I can take a nobrainer approach and give my design a "spice pass" if the FFT doesn't peak beyond 200uV. ?? D from BC

that

the LISN usually has 1k pull-downs, which ge6t shunted by the speccy 50R (and of course 1k//50R = 1k (ish))

part-way between peak and average. somebody might be able to supply the details.....

the graph has dB on the vertical axis and log(f) on the horizontal. this refers to a straight line between 66dBuV @ 150kHz, down to 56dBuV at 500kHz.

so the line starts at 66dBuV @ 150kHz, slopes down to 56dBuV @ 500kHz, stays flat to 5MHz then jumps up to 60dBuV between 5MHz and 30MHz.

e.g.:

\\ \\ \\ _____________ \\___________|

not, of course, even vaguely to scale.

LOL :)

assuming, of course, you have correctly accounted for ALL of the parasitics, AND your edge transitions are exactly right.....

in practice it works fairly well for conducted emissions, which are mostly due to the (LF - MF) spectra of the SMPS input current, and you can usually make a reasonable stab at the parasitics.

radiated is all about the HF wiggly bits, and SPICE aint much help here. again you can model some of the parasitics, but mutual coupling rears its ugly head at HF (there was a good IEEE trans. power electronics paper last year that showed a conventional X cap - CM choke - X cap filter HF performance was dominated by the mutual coupling between the two caps.....) and that is much, much harder to include in a simulation than, say, the ESL and ESR of the main DC bus capacitor.....

Cheers Terry

that

?? Doesn't // mean parallel resistors? Shouldn't that be

Are you saying that the schematic should be:

LineDUT | | 0.1uF | +--------+ | | 1k FFT (50 ohm terminated) | | Earth GndDUT | | 1k FFT (50 ohm terminated) | | +--------+ | 0.1uF | | NeutralDUT

This looks more correct...The noise currents flow through ~50ohms.

Ohhh great :( X cap to X cap magnetic coupling... There's something I don't look forward to.

D from BC

so that

oops. yep.

bingo.

So...(in spice). I check if FFT A is within FCC limits.. Then.. I check FFT B is within FCC limits... And...that' it..?

LineDUT | | 0.1uF | +--------+ | | 1k FFT A (50 ohm terminated) | | Earth GndDUT | | 1k FFT B (50 ohm terminated) | | +--------+ | 0.1uF | | NeutralDUT

If so...great and thanks for the conformance info.

I dunno why I had some Googling trouble digging up this material on the web and in the news achieves.. I thought it would be easy to find. D from BC

so that

To model wall wart in spice use a transformer to obtain the open circuit step down ratio, and a series resisitnace in the secondary that provides a current limiting by dropping on the output side. Fast and coherent! marco

D from BC snipped-for-privacy@comic.com posted to sci.electronics.design:

This link may be useful:

I think you want 47 CFR 15.

and then you build a real one, and test it with a real speccy, and see how close your sim matches reality. Like I said earlier, the HF stuff is all about edges (hard to model accurately) and (often subtle) parasitics.

I've done this analysis for a few customers, not to design in EMC compliance, but to show that there is no way in hell of it ever passing, so dont waste money testing it.

I also do this for my designs, but dont pay much attention to the HF stuff. you basically get one of 3 results:

- not a chance! e.g. no input filtering at all.....drastic changes required

- absolutely piss in - in which case you have probably done something wrong! EMC is never trivial.... {sorry about the antipodean slang; means "pass with plenty of margin"}

- looks OK, in which case the design has got a reasonable chance of passing; if it fails, it ought to be able to be modified to pass without any drastic changes. at this point, good EMC layout is probably what determines pass or fail.

Cheers Terry

I've yet to do that...but it's not quite what I had in mind.

My post title is bad...I should have entitled it "LISN and FCC SMPS Compliance in SPICE"

SMDA (So Many Damn Acronyms) :P

Which I think also stands for surface mount device package A. D from BC