Software Controlled Crystal Oscillator

'U04 = UNBUFFERED inverter... the most difficult part in the ON-Semi

I would think that ONE step, pin as output driven 0 to 1 and back for the minimum possible time would make the xtal ring. As fast as possible after this impulse function is complete, switch the pin to input mode and measure times when zero-crossing is seen. If the pin is directly connected to the xtal, "DC bias" is not the correct term. What matters is that the FULL 5V (or output swing of the micro) is seen, which is NOT good even for crystals, and almost guarantees permanent damage to a tuning fork type. So, take that pin and use a 10:1 divider for 500mV drive Justin Case a tuning fork type is being tested (cannot say if that is too much, it might be).

pin *----/\/\/-----+---+ | | / | xtal \ === / | | | *--------------+---+ GND

As you say, the SW monitor would be used to determine when the next impulse would be needed.

Doesn't Don have a "magic sine" generator that uses pulses of some sort? Been ages sine i saw that zip by..

So...figure in the delays; maybe need to add an extra NOP or so to refine impulse timing..

There is usually an inc by one instruction and a conditional jump on bit test. It may give you finer granularity in a tighter loop.

I have used this trick to get accurate audio frequencies (with terrible phase jitter) out of relatively slowly clocked devices.

I guess it depends what tests are easy on the CPU if you only have sign and overflow then adding a suitable constant is the way to go.

You don't have to hit the immediate next top dead centre with a pulse but you do have to hit it reliably spot on to reinforce the oscillation. John was right - starting it up is the tricky bit. Some kind of chirp approach would seem the most likely. How close to the crystal fundamental resonance does a signal need to be to excite one?

Will a hard driven crystal entrain at say 1000ppm away from resonance or do you have to get pretty close to spot on? Also which resonance will it lock on to when driven in this sort of fashion?

No. We are talking fractional Nops here or more likely two paths of a conditional branch that differ by one cycle every N times round a loop. It will all have to be self tuning software timing loops (possibly with the ability to correct for thermal drift too). Tricky problem...

That's what the 1.5 ns instruction is, a counted loop control instruction called unext. There is no way to get finer granularity, but the dithering seems to work ok.

There's the rub. There is *no* zero crossing detect. This is a digital input pin and the threshold is at some value near Vcc/2 or 0.9 V.

Is 1.8 V too much?

I'm not sure this is really useful in terms of a timing reference; the usual scheme is to generate a square-wave logic train that is triggered by the small crystal 'echo'. That crystal contribution is a sinewave, because the higher harmonics of the (square-wave) drive signal are damped more than the fundamental, and the whole loop is gain-starved. The result is a square-wave from the logic output, and a phase-lock to the crystal contribution. It has long-time coherence from the lightly coupled rock, and sharp edges from the relatively high-power logic drive.

Listening for a ring-down does NOT have long-time coherence (the crystal ringing phase gets reset on each input pulse) and doesn't have high-power logic drive to an unvarying signal (I'd expect the phase of the output to be amplitude-dependent, which means the resulting tone burst drifts in frequency).

It'd work better if you used an LC tank. Harmonics are less important, and even a small LC can store lots of energy.

It would depend on how you drive the crystal. If you drive it on the half-cycle, with a high-going and low-going pulses, then the edges will happen at roughly the +/- 90-degree marks. If you just drive it with a positive pulse the crystal voltage will drift up to VSS and there won't be any AC drive to the crystal at all.

So if it's working, the edges will be around the 90 degree points -- any deviation from this will depend on the chip's threshold voltage.

If you're running the oscillator in parallel mode then the crystal itself will look inductive -- but you need to pair it up with the specified load capacitance.

Yes, but the correct phase angle is 90 degrees, which is 1/4 of a cycle.

It will increase the phase noise introduced by the processor, giving you a tradeoff between power consumption and timebase quality.

How much of this thread have you read? Please go back and read the initial post about what the circuit is doing. I think you misunderstand the difference between initialization and continuous operation.

Maybe you just need to build the damned thing and see how it works?

I don't get why you refer to the "half-cycle". Why would that be the threshold crossing invariant of amplitude?

Someone pointed out that the amplitude dependance of the phase of the drive would lead to lots of phase noise. I think this is correct. Especially when you consider that the voltage on the crystal doesn't provide the output directly. The clock will come from the processor activated by the edge detect. Assuming this clock is only needed internally, this timing reference is passed around internally between the processors. Due to the very low latency of instruction execution there is very little phase jitter added other than perhaps the variability of instruction execution time I suppose. I guess once you enter the "soft" domain the idea of phase jitter is hard to maintain. This might be problematic for an application which is very phase jitter sensitive.

By 90 degree points, I assume you mean the zero crossings of a pure cosine wave with no DC artifact? Otherwise I am not at all clear what phase angle you are referring to.

Correct meaning what? 90 degrees on a sine wave is the point of maximum amplitude. Is that what you mean? But that may or may not be 90 degrees from the threshold crossing.

It's already built. The question is how to build it well. If you don't understand it, fine. No need to get huffy about it.

One does not need to impulse drive EVERY time the xtal goes thru zero; every 3rd time, or 17th time would work....in fact changing that N to a lower value would be the equivalent of decreased drive.

• As Einstein used to say, it is all relative (aunts, uncles, etc). In this case, i would define "zero crossing" as being the point where the slope of the (presumed) sine is maximum positive/negative.

• For a tuning fork, 500mV may be too much. ** COPY OF POST AGES AGO: Plug crystal into appropriate socket; each has its specified load. The drive resistor shown is the maximum value that allows all frequencies of a given type to oscillate; some frequencies work with higher R values (less drive). NOTE: in *all* cases the frequency is higher than marked (expected) value. Made using a 74AC02 which oscillates near 140Mhz with no Xtal plugged in (amplitude about 1V pk-pk at 5V supply).

Xlo (Khz) 10M Marking | Measured +-----/\/\----+ --------+----------- | | 32 | 32.7711 | |\ | | 32.7710 +-----| >o----+---+ | 32.7721 | |/ | | --------+----------- | \ | 100 | 100.0033 | 680K / | | 100.0042 | \ | --------+----------- | Xlo | | 200 | 200.0951 +-----o o----+ \ --------+----------- | | / 6.8K 1000 | 1000.386 --- 10p --- \ --- 22p --- | Xhi (Mhz) | | | Marking | Measured | V | ----------+----------- | Xhi | 2.000 | 2.000188 +-----o o----+---+ | 2.000179 | | ----------+----------- --- --- 3.579545 | 3.580152 --- 18p --- 18p ----------+----------- | | 10.000 | 10.003115 V GND V ----------+----------- 12.000 | 12.007229

Depends on if you are talking about the start up period or the maintenance period. During startup I would assume the fasted start up would be with a nearly continuous drive even if it is dithered a bit. No?

In maintenance the drive rate can be reduced possibly, depending on the drive vs. the dissipation. I'm not sure of the advantage of fewer pulses of longer duration. I would think the crystal would be more stable with drive on every cycle rather than letting it wind down some before popping it again. But there is a lot going on and I don't think it has been analyzed well enough to say for sure.

Ok, great. Now we are on the same wavelength so to speak. The input of the pin will not have a zero crossing detect. There is no reason to believe the zero crossing will be coincident with the input threshold crossing.

But you are talking about a continuous drive of a 500 mV sine wave. A drive of 1.8 V for 2 ns is not likely to hurt a crystal from over drive.

Great circuit, but it is continuous. Not terribly applicable to an impulse type of drive, no, yes? Also, I'm unclear on the reason for the 22 pF cap in series with the Xhi. Is that mainly to reduce the capacitance Xlo sees? What does it do to the Xhi circuit?

Actually I have been wondering about the best drive waveform to match the crystal instead of the more obvious square wave. Again it depends what you want to do. Two obvious strategies exist:

Closest approximation to pure fundamental at f0

which is approx --------01111110 or assymetric ----1110

This has the effect of suppressing the third harmonic and gives a better coupling to the fundamental mode. It also neatly avoids charging the capacitive load of the xtal up to Vcc.

Closest approximation to first three harmonics f0, 2f0, 3f0

which is approx ---101

Where - = tristate

The latter means you are in effect searching three frequencies at once albeit with somewhat reduced efficiency.

Once the thing is ringing properly you want to kick it as infrequently as possible to sustain the oscillation (same as you would do with a regulator pendulum clock). The crystal is a way better frequency reference than the crude exciter pulse.

You might find it useful to read up on regulator clocks since they are the direct electromechanical analogues of what you are trying to do here. The hit & miss synchroniser being one such mechanism that might work for you if you can replicate the functionality in code.

NB this thing in its day was as good as a modern ovened crystal clock good to about 200us/day drift.

Actually one other thought given that your zero crossing detector is sat at about 0.9v is to make the crystal not referenced to 0V but on top of a forward biassed diode voltage drop or two.

Then the crystal doesn't have to be driven quite so hard for the chip to see it is oscillating. As someone else has pointed out an LC tank will hold more energy and might be easier to make fly.