That description leaves out so many critical layout concerns that it is pretty pointless for me to put any more effort into your problem. By the time I have asked you about all of them and you have answered me, you will have given up enough information that anyone skilled in the art could not only effectively duplicate your design, they could improve on it.
Best of luck to you.
-- John Popelish
I believe this is the first time you've mentioned the presence of a 'sensing resistor'. The referenced app circuit doesn't use one.
Please elaborate.
RL
......and you say the board design has been used for two years, but you're open to suggestions involving IC replacement?
Have you changed your fet driver lately. What type is it?
The leading edge blanking issue is not going to go away.
Early drive PW termination can sometimes be induced by gate current in the current sensing resistors, when they are placed in the source lead of the fet. MOS drivers with lower output drive impedance aggravate this effect, so check that this has not 'improved' lately.
The effect can be reduced (at turn-on only) by capacitively decoupling the driver IC positive supply pin to the fet source terminal, directly. Integrated drivers are extremely fussy about how they like to be decoupled, however, so you'd have to keep your eyes open for other problems. MOS drivers with lower drive capability(ie higher output z) are less fussy. The technique is better suited to simple emitter-follower buffers.
RL
In article , legg wrote: [...]
Yes much clearer.
If the power supply is part of a larger system, the AC bypassing of the mains and internal supplies for the whole product should be examined. The capacitors from the mains to the chassis of the power supply also from the output to the chassis, can help the supply when it is considered in isolation and make matters much worse when the whole product is considered.
If the supply gets its mains connection through longish internal wiring and the chassis of the power supply are not a near zero impedance, the capacitors can serve as a path to place large amounts of RF onto the power wiring.
This usually makes life a bit easier.
-- -- kensmith@rahul.net forging knowledge
In article , legg wrote: [...]
Also: Did you by the current sense resistors from a different supplier? Did the bypass capacitors change?[1] Do the ones that don't work have the inductors arranged in some different way?[2]
[1]Just because the nominal value of a capacitor is 0.1uF doesn't mean that it is even close. [2]Remember that toroidal inductors don't really have zero external field in real life.Remember to place an impedance in the supply connection. Without it, the current sense circuit ends up with an RF connection to the supply voltage of the switcher chip.
Also, if the FET or the driver is oscillating, and RF bead in the gate lead can suppress it.
[...]The NPN, PNP emitter follower circuit can pass truely stupendous amounts of current when pulling the MOSFET on. This is because the NPN is biased on and charging the gate capacitance at the instant the MOSFET starts to conduct. When the MOSFET starts to conduct, the reverse transfer capacitance causes the gate voltage to stop rising briefly. During this time, the NPN's current is quite large.
-- -- kensmith@rahul.net forging knowledge
I agree with your logic regarding duplicating the design. But please understand that to post the layout would be to share the intellectual property of my employer. That is simply something that one does not do. I do appreciate the helpful advice that you and others have posted. I will continue to review the information.
TP
The driver hasn't been changed. It is a IXYS IXDD408SI. Output resistance .8 ohm, rise time 14ns, on-time propagation delay 38ns. The output is connected to the gate through the parallel combination of a 1nF capacitor and a 15 ohm resistor. This is to initiate turn-on quickly but finish more slowly. The reason is to reduce noise. A switching diode brings an additional 10 ohm resistor in parallel to speed up turn-off only. There are snubbers everywhere for noise control including one from gate to source, a 10 ohm in series with a 2.2nF.
That is an interesting point that had not occurred to me. In this particular case, the turn-on is as soft as possible with the added gate resistor. The effect of the gate capacitor should occur before the leading edge blanking has expired. The LTC 1871 provides approximately 180ns leading edge blanking.
TP
IXYS seems reluctant to provide an electronic data sheet on it's website - the number is mentioned only in an EV board note, so I cannot comment on this device specifically
The 0.8R driver resistance that you note is on the extreme low side of my experience with these animals. Providing that ground bounce that is self-generated is not obviously interfering with output states, the only concern is the control of gate current externally - which is obviously being attempted, by your description.
The series and shunt fet gate component combinations sound a little convoluted - the capacitor in the 1nF/15R combination seems particularly counterproductive to the control of switching speed or noise. How long ago was the performance of this section verified or validated?
You can monitor waveforms on the resistor and at the IC sense pin to see if they are as expected, at any time. Though the subharmonic oscillation may seem strange to you, it is only really strange if the chip is not responding logically to the inputs provided to it.
RL
The sepic topology of the app note uses a coupled inductor.
1) The sepic inductor coupling is often intentionally degraded to reduce ripple current. This would require careful fab notes to control winding positions on a toroid. Loosely-coupled windings result in increased stray magnetic fields that can couple into board traces. The severity of coupling increases as the case compresses the stray fields into a smaller volume.More closely coupled winding methods will increase interwinding capacity - which aggravates'primary' turn-on current spikes and noise feedthrough.
2) What controls are maintained on the layering/sectioning and terminal orientation of this part?If it has four terminals and is physically reversible without generating a phasing error, primary/secondary layering can be inadvertently altered. Noise on one winding or layer is not the same as another winding or layer. Switch them around and the noise flora and fauna will alter in the vicinity. If possible, the quieter sections should form outer layers, or be located in unavoidable proximity to other sensitive circuitry.
3) Is the logic power taken from the output power winding or from an added auxiliary? The 3R5/0u47 supply filtering used in the IXYS driver EV board should be probably be present, independant of the bulk storage on this rail, whether or not it makes sense to you.Though the driver may have rated delays and rise-times, and the controller may have a nominal LEB duration - be reminded that these are applicable to the application circuit arrangments only. Without knowing how the LEB duration is derived, you cannot know the effect of the reduced load capacitance presented by the added external drive buffer.
With resistive gate current limiting, you should be able to measure the effect on switching speed, to see if anticipated LEB covers the neccessary time interval.
Intentionally producing the faulty performance should be the first priority i troubleshooting the behaviour. In the fault condition, the short drive pulse can be examined to see it's relationship to output drive, gate amplitude and chip pin signals make sense.
RL
I have placed the IXYS data sheet here:
About a year ago. The 15R resistor slows down the turn-on considerably and substantially reduces the noise at the output. At maximum load and minimum input voltage this can be a problem because it eats up too much of the available duty cycle time and the circuit can become unstable. The parallel 1nF capacitor brings the gate voltage up to threshhold quickly so that the overall turn-on time is reduced without affecting the speed of turn-on during the portion where conduction is being established. In other words, the cap speeds up turn-on without adding noise at the output.
I can monitor the sense pin though the probe picks up a lot of noise. I believe the short cycle is terminated during leading edge blanking so the sense pin should not be a factor at that time. The Ith (error amplifier) pin cannot be probed because it disturbs the operation of the circuit.
It also is buried in the IXYS alternate site, where IXYS search can't find it.
I understand it's intent, however it's presence defeats any resistors listed as being used so far, just as effectively, during all other switching periods. A solid R value gives a calculable and measurable limit to dV/dT on the drain (and peak gate drive current in the source), under hard-switching conditions.
As the drain node is widespread (- inductor body, heatspreader, coupling cap and output inductor/rectifier all-included -) this is a major noise generator for capacitive current, vertically polarized to all conductive hardware. The other capacitive source is diode reverse recovery - which can do things above 10MHz that also make it a horizontally polarized threat (loop current) as well.
The Isense pin is the first suspect. Try probing both though a 1K, or even a 10K resistor. As HiZ inputs, they have to function predictably in the real world. Don't forget the feedback pin.
If you can't see it, you're still just guessing, in your reassurances to others. That's what verification is supposed to avoid - there should be a picture or even a hand-drawn sketch with your signature on it when this issue is eventually closed, with a brief note explaining why it illustrates that problematic behaviour is proven not to be due to x y or z. The next guy that comes along can, in the worst case, duplicate it quickly with this guidance.
I was going to suggest a capacitve load on the controller's drive ouput, assuming that the reciever would act long before the input rose to full amplitude; but the buffer input minimum high logic level is specced at 3V5, which doesn't allow it much advance on controller internal sensors (suspected as being leb-determinant), with the low amplitude driver voltage produced here.
RL
Thank you for your advice. The current production run is actually going well but we are reserving one unit that exhibits this problem for study (when I can get the time to do it). I will try to get some scope images of the sense and FB pins to compare with the erratic gate signals.
There is one thing here that I don't understand. What is meant by "leb-determinant" in the last paragraph?
Thanks again.
TP
Leading edge blanking is present, according to your information (not in the spec sheet, by the way) - the method of its generation is unknown.
It is pure speculation on my part, based on the repeated simplicity of the published applications (gate resistors - nowhere). Guess is that the unspecified leb periods were being determined by loaded rise-times of the output drive terminal. This would obviously be one simple way of detecting completion of drain dv/dt - while still providing quick short-circuit protection. (A shorted load produces no dv/dt effect on the gate).
Though the circuit may exhibit modes of subharmonic oscillation, there is no reason why this occasional chaotic behaviour would prevent basic function, in most applications.
Undocumented magnetic component construction and placement, being predominantly manually-controlled for toroidal shapes, probably offers the biggest opportunity for inadvertent changes to creep into an established design, providing that manufacturing methods and material quality haven't altered elsewhere (ie capacitor types, board vendors, soldering processes, lead-dressing etc.).
RL
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