SMD TC??

The OPA378 (my fave) is about 200 pA max. An LT1043 gizmo might be more suitable, especially since it can be synched to the ripple waveform. A bit of dorking of the phase of its clock with code might be one way to extend the vernier/bootstrap idea to the filter--there's some clock phase that gets you the exact right answer for a given ripple waveform, and if the ripple is small anyway, errors in that position will be less serious.

That does introduce some more dependence on the capacitor value and its voltage coefficient.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Reply to
Phil Hobbs
Loading thread data ...

The falling and rising edges don't cancel exactly except at one code, but as long as they don't start to overlap their contribution is just a very small fixed gain and offset error.

For straight-line edges, outside the overlap region, I think you get

Positive DC = code/(N*(1-(t_f + t_)/P)) + 1/2((t_f -t_r)/P)

Assuming that the edges don't change shape with code, you get 0 and Vref at the ends of the travel, and some nonlinearity adjacent to there due to the glitch, so the slope in the middle is a little bit higher, but it's still linear in that whole range.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Reply to
Phil Hobbs

In other words, this transfer curve, minus the low frequency phase shift:

formatting link

The ends get bumped off when the PWM code is within threshold of the comparator, equivalent to:

formatting link
which has hysteresis on the comparator and thus will have a certain minimum pulse width.

Simple way to address it should be, if you get the slopes equal with rapid settling time, and make the first and last codes (i.e., minimum and maximum pulse widths) at least wider than the total settling time, you won't have "runt" pulses because then all codes look the same aside from PWM.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Reply to
Tim Williams

across

100K, 1%

R3

=A0100K, 1%

=A0O---------+---/\/\/---+-----> Vout

=A0 =A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0--- Cf

=A0---

=A0 =A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 =A0 =A0=3D=3D=3D

needs

=A0R3, 0.05%

=A0O-------+--/\/\/---+---/\/\/--+-----> Vout

=A0 =A0 =A0 =A0| =A0 =A0Rf =A0 =A0|

=A0 =A0 =A0| =A0 =A0 =A0 =A0 --- Cf

=A0 =A0 =A0 ---

=A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0|

=A0 =A0 =A0|

=A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 =A0 =3D=3D=3D

=A0 =A0 =A0 =A0 =A0|

=A0 =A0 =A0 =A0 =A0|

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 =A0 |

=A0 =A0 =A0 | | R7

1000 x R3, 0.05%

=A0 =A0 '-'

=A0 =A0 =A0 =A0|

=3D

in

contribution

or

1,000.

better

Y5V

the

Thanks, i don't want to think about the number of times i have stumbled over similar issues. Just the same, with coarse/fine dacs some overlap = in the bits represented and using the fine dac to correct the linearity issues of the coarse dac works pretty well. You will have to = characterize the coarse dac and that costs time and money. If you have more that a = few to build you had better automate it. It becomes imperative to know exactly what kind(s) of linearity you really need, including temporal properties.

?-)

Reply to
josephkk

[...]

I must be missing something here, it looks to me like it should be perfect (outside the overlap range right at the ends).

The area of the orignal rectangular waveform lost from t_r is added on again by t_f (but they do need to be equal).

The onset of overlap is when t_r = t_f = t_on. The output just manages to slew to full scale before starting to turn off again. This looks like a triangle with a base of width t_r+t+f = 2*t_on. This has the same average as the rectangular pulse width 1*t_on.

--

John Devereux
Reply to
John Devereux

e
f
s

It looks fine to me (on paper) too. You don=92t care too much exactly what the slope is, as long as the rising and falling slopes =91exactly=92 match. Perhaps that=92s hard to do in practice, making the cure worse than the disease.

George H.

Reply to
George Herold

Hi George,

It is still a big improvement over the idea that any non-zero slope is an error. As already discussed we already need to match the upper and lower driver resistances pretty well. So this should also tend to match the slopes well too!

Yes, I am not actually proposing deliberately slowing down the transitions (as you suggested above). But it works for the natural transition slew-rate too I think.

--

John Devereux
Reply to
John Devereux

Say that the rising and falling edges are exactly one clock cycle each.

Between codes 3 and N-3, everything is precisely linear. At codes 0 and N, the output is 0 and Vref, respectively.

Code 1 gets you half a rising edge and half a falling edge -> triangle of height 1/2 and base 1 so area = 1/4.

Code 2 gets you one full rising edge and one full falling edge -> triangle of height 1 and base 2, area = 1. So:

Code V/Vref

0 0 1 0.25/N 2 1/N ...

N-2 1-1/N N-1 1-0.25/N N 1.00000000

In between, it's precisely linear, so the slope between 2 and N-2 is

Vref*(N-2)/(N-4)

which is a bit higher than Vref/N.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Reply to
Phil Hobbs

Why half a rising edge? You said rise time was 1 clock so it should be a full height triangle width 2 (1 to rise, 1 to fall). Area = 1 as desired.

I make it a full rising edge, one clock of full value voltage then a full falling edge. Area = 2.

--

John Devereux
Reply to
John Devereux

There's no reason to ever use the end codes. Design with a little extra range and cal down.

--

John Larkin                  Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Reply to
John Larkin

Yes of course - could be less than 1ppm anyway (ns edge rates vs ms periods).

--

John Devereux
Reply to
John Devereux

[...]

Well???? What do you think? C'mon -- a successful correction to Phil Hobbs goes on my CV! :)

--

John Devereux
Reply to
John Devereux

Agreed.

||

tr h tf ||____________|| _ Vh | /| |\ | / | / | | \ | / | / | | \ | / | / | | \ | l / ....|/ \|______/ ____ Vl

||

Where t(code) is the commanded high time t(pwm) is the pwm period

Vh * (t(code) + (tf-tr)/2) V(code) =3D -------------------------- t(pwm)

A difference in propagation delay tpd(H->L) - tpd(L->H) has the same effect.

Yep.

Yep.

Yep.

Bootstrapping the output almost eliminates the load on Vref, which effectively kills the Vref ripple current error too. The high DAC timing error effect is still annoying.

It seems most people who split PWM DACs overlap the two DACs' ranges, then calibrate any errors out. That's a nuisance. If gates' timings matched we could possibly generate a compensating voltage, but I ... don't ... really ... trust ... that.

-- Cheers, James Arthur

Reply to
dagmargoodboat

Yup. The Fluke calibrator manual that John linked splits the DAC into two overlapping DACs, calibrates them individually, and combines them.

They spec 0.2ppm linearity, but one wonders how well that holds if/as the instrument's temperature slews. Their PWM comes from an 82C51 timer clocked at 8MHz, then *optically coupled* (!). That can't be very temperature stable. Fluke regulates the substrate temperature, but still...

-- Cheers, James Arthur

Reply to
dagmargoodboat

Oh yes, of course it does, excellent.

--

John Devereux
Reply to
John Devereux

I once showed Phil something he didn't know. It was where we keep the bottle opener or something. I also introduced him to fried grits, which he very politely said that he liked.

--

John Larkin         Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro   acquisition and simulation
Reply to
John Larkin

Well, still nothing...

Let us simply agree that I am the superior theoretician and we'll say no more about it.

--

John Devereux
Reply to
John Devereux

My classical Netscape 4.79 newsreader got wedged, so I didn't see the rest of this thread until I deleted SED and downloaded it again. Netscape doesn't like groups with 900,000 messages in them, but it's still much better than Seamonkey or Thunderbird. (Must be some N**2 algorithm deep down somewhere--probably bubble sort, if I remember the dotcom days as well as I think I do.)

The two main reasons that I frequent SED are that I like shooting the breeze with engineers, and that I learn stuff. I have a directory with several hundred saved SED posts going back some years, because there's a lot of lore available here that you don't find elsewhere, at least not in the same pithy form. (Some of it I even repackage and resell, as I do with stuff I learn elsewhere.) It helps to look for what attracts honeybees rather than flies.

In the present case, you're quite right--I was thinking of the mythical odd-order case, where the transitions pivoted about the center of the slope. It turns out that the case where the rise and fall times equal one bit period each is the singular one--faster than that, the linearity is OK, but any slower and the nonlinearity sets in.

The key point, as in logic-based phase detectors, is not to let the slopes intersect.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net
Reply to
Phil Hobbs

stumbled

overlap in

characterize

few

Calibrators are intended to be use in very benign environments.

?-)

Reply to
josephkk

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