1,3,5 and 2,4,6 aren't common-centroid, they're shifted by one whole pitch. You find a common centroid layout by summing the indices, which in an equally-spaced layout is the same as taking the average positions (i.e. the first moment).
1+3+5 = 9 centroid = 3
2+4+6 = 12 centroid = 4
More symmetrical layouts with more resistors can get rid of higher-order gradients, just like the weighted 74HC4017 does with harmonics, but it isn't as important in general.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
If the resistor is on an alumina substrate, it's probably more important to manage the heat flux than it is to get the resistor layout just right--if there's a heat source nearby, or the thermal resistances on the pins are very different, even a common centroid layout won't help much. It's a first-order help, like biasing an amplifier at its maximum-dissipation point to avoid thermal tails on the step response.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
Fun time, thanks again. I've got no circuit that'll need a common centroid design.
Currently, it's an S-V filter, mostly inverting opamps. I've got a choice of putting the R's at the source or the destination. I figure right at the source is better, but I'm open to other opinions.
OK, after six months, six or seven days most weeks (and, due to committing to a not-so-clearly defined project, mostly for free), I've just gotten my gadget in shipping-shape.
C1-R4 re-create the same currents as flow in R3. Effective switch resistance (R1, R2) is lowered by about two orders of magnitude, allowing us to reduce R3 and lower the output impedance.
Filtering the 100Hz PWM to 1ppm takes 14 time-constants = 140mS.
So, Fig. 3 is a working solution. It's linear and accurate, but needs a hi-z buffer amp and it's slow. A 16-bit version could be faster, with lower-z output. Or, splitting the DAC up into two sections improves both those properties too.
If the upper and lower DACS cover 1,000:1 each, we could lower the clock frequency to, say, 10MHz, pump it with a uC, and still have a
10kHz composite waveform that one-pole-filters to 1ppm in 14 * 100uS =
1.4mS.
The R7-R3 ratio is critical to absolute accuracy and monotonicity. The top DAC divides Vref accurately into 1,000 parts, so a 1% error in the R7-R3 divider ratio represents an error of 1 part in 100 of
1/1,000th, or 1 part in 100,000 overall. 0.05% ensures 0.5ppm.
Likewise, to ensure monotonicity to 1ppm, the lower DAC's contribution of 1,000 lsb's cannot be off by >1 part (lsb) in those 1,000 lsb's, or
0.1%
The low DAC represents a small, code-related d.c. load on R1, R2 via R7. That needs to be either kept small, or compensated.
Back to the topic of this thread, the effect of T/C errors in the divider resistors is reduced by the divider ratio, a factor of 1,000.
So, there's a stable, accurate, 1ppm PWM DAC made with non-critical parts.
Bootstrapping a PWM is a cute idea. I might use a second PWM output rather than the drive signal, because the levels should be a lot better controlled, but that's a nit.
The other thing is that you still need nice fast, linear capacitor behaviour if you're going to put any sort of AC on the output. A Y5V would ruin your whole day, and even an NPO might have its issues at the
1 ppm level.
And then there's the resistor nonlinearity, which would be fun to measure--build two of your circuits, connect the outputs together, and run them with their codes offset and complemented, so they should sum to, say, VRef/3, and look at the residuals. (Picking an off-center value gets you the odd harmonics as well as the even ones.) Old-school metal films are pretty good, with the quadratic term specified at
10**-7/V or less, but much better in practice. I haven't seen specs for the newer weaselly-sounding "thin film" types. (All the ones I know about are actually metal films, but somebody might try sneaking in tantalum nitride or tin oxide or something like that.)
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058
hobbs at electrooptical dot net
http://electrooptical.net
The Vpwm(hi) amplitude (aka Vcomp) has to be accurate, that's true, and hence specified in the diagram. I assume it'd be derived from Vref or vice versa, then buffered.
It doesn't have to be hyper-accurate--the total tolerances of Vpwm(hi), esr(Vpwm(hi)), and R3 and R4 set the limit on the bootstrap performance, that's all. 1% would be great.
Worse, I initially analyzed the filtering as an "impulse settling to
1ppm problem," but it's clear I should've been thinking in terms of ripple rejection instead. So, for 120dB ripple rejection, something like a passive multi-pole filter is a lot better than the single-pole shown. Taking a huge bite out of the ripple in earlier stages should ease the final filter cap requirements too.
There are a few more basic gotchas too. I designed it on paper. Trying it out on LTSpice, I see a few gremlins crept in--bad assumptions.
The worst is that, for absolute accuracy, I forgot when splitting the DAC in Fig. 4 that the top DAC still has to split Vref into 1/1,000th chunks *accurate to 1ppm*. Ooops. So, even at a reduced 10KHz PWM rate, switch speed requirements are not relaxed; 3nS is 3nS/100uS, a
30ppm error that is not reduced by the architecture, as I had wrongly assumed it would be.
I think there's a clever way to compensate that, but the easy, clear way is Fig. 3.
Not exactly brain-boggling. The circuit diagrams aren't clearest and most comprehensible I've seen, but 26 figures and a hundred pages of circuit digram is respectable - rather than over-whelming - complexity. Even John Larkin would be hard pressed to draw that all in two and half weeks, let alone design the circuits being drawn.
Were you thinking of the simplified diagram 2_17 at page 125, or did you have something more complicated in mind?
-- Bill Sloman, Nijmegen
.highlandtechnology.com=A0 jlarkin at highlandtechnology dot com
I have been looking at this too! Like you I have looked at the various gates for this (I started a thread about it last year I think). I also found the ISL43L210
This is not only a sub-ohm switch but has the resistances matched to 2 milliohms! Low voltage though.
But your bootstrap idea is more interesting.
I don't like this so much, since we require precision resistor matching. As you realised downthread I think. The single-PWM approach is nicer if it can be made to work since it is independent of resistor accuracy. Except your bootstrap idea, but tolerance does not need to be tight there.
I wouldn't. It's old and klutzy. There are better ways to do it now.
We have an HP calibrator of comparable performance, same vintage, and it's much simpler.
Why not several very good references, supervised and averaged, a coarse/fine dac pair, and a 24 bit delta-sigma ADC? Close the loop on that. It could all be put on a temperature-controlled block, like this:
formatting link
formatting link
Voltage dividers can be made self-calibrating, as can most things that are inherently dimensionless.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Tom Bruhns from Hewlett-Parkard - later Agilent - used to post here. His last post here seems to be December 30, 2008. I was quite fond of HP's Techical Journal, and when I was working on medical ultrasound at EMI Central Research (1976-79)we were scared silly - unjustly as it turned out - of their phased array machine.
One of my colleagues at Cambridge Instruments did a calibrator for Datron in the UK. It took longer that his bosses liked, which was why Dave ended up working for us. When he described what he'd been doing - including (amongst other things) a ratio transformer to get really stable division ratios and an integrating 24-bit A/D converter where he'd ended up using a Teflon(PTFE to you) dielectric capacitor to minimise charge soak, then had to go on to minimise the extent to which the capacitor ever accumulated much of a voltage difference - my boss and I both (separately) reckoned that he was somebody we really ought to hire. We were right.
Hey, that's pretty cool. Their "series" and "shunt" "linearity" circuits amount to something like my bootstrap, but mine's more linear (their currents are static; mine track with duty cycle).
They generate the two PWM modulations with two sections of an 82C51, clocked at 8MHz, and coupled to the switches via fiber optics. The prop. delay variance is huge, with no obvious allowance. They must calibrate that out.
That's excellent. Keep in mind that Ron varies with voltage; the matching spec applies under equal conditions, but the applied voltages will not be equal. Poking around Digi-Key your choice is tops, with other choices too. So, that function is multiply-sourced.
Using a bootstrap and a hot switch opens even more options, like R3 =
10K, a 10x impedance improvement.
I don't think there's any requirement for ultra-precision matching. The lower DAC's entire weight is only 1000 lsb. If it's off by 0.5 parts in 1000, that's only 1/2 an lsb=0.5ppm on Vout.
But, the timing of the upper DAC is 1000x more critical than the lower DAC -- the hi DAC timing has to be good to 1ppm. Out of 100uS in my
10KHz example, that's 100pS. Ouch.
The single-PWM is definitely simpler. In application, though, I'm concerned about the high output impedance. The load has to be at least 100K/1ppm = 100G ohms to preserve the absolute accuracy, or highly stable if you're going to divide it down by some stable factor.
Anyway, PWM seems a perfectly reasonable, straight-forward way to make pokey 14 or 16-bit DACs.
Oh yes you are right, I thought because you were summing them R3 would need to be 1ppm. But that is not true. So there are no precision parts needed.
Hmm. There are several aspects to the "timing" here. One is the placement of the edges, the other is the transition time. As I think Phil H pointed out you don't need 100ps edge transitions; in fact the error in the falling edge can cancel the rising one. I think it just needs to be symetrical.
Of course the absolute frequency of the PWM is not critical either.
As for jitter, I think any random jitter will get averaged out.
The thing we would need to avoid is a code-dependent error.
The other thing is supply ripple, which is "code-dependent" and will get worse with your lower value resistors (which I agree are highly desirable otherwise).
So my "clever" contribution is to make the current constant by using an inverted copy of the PWM, feeding a load of the same R into a buffered copy of the output.
Yes it's a problem, the chopper opamps don't have the pA input currents AFAICS.
Nice ideas James! As perhaps a silly idea, could you give up the sharp edges and settle for 'well defined' slopes. Drive a current into and out of a cap (at some longish time) so the transitions were always the same?
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