Silly resistor values

Caribbean accent? SCNR :-)

In my case there are mainly two reasons:

a. The device must have its personal regulator/filter/whatever and other engineers and also technicians need to understand that. This is much easier when present at the symbol. Otherwise they might draw the wrong conclusions like "Oops, +12V is missing, lets take the main power supply apart" while in reality the local regulator was gated off for some reason.

b. I often have situations where, say, an opamp or comparator switches the supply of another. This can become next to impossible to understand by other engineers, especially younger ones.

Cadsoft Eagle allows a very nice flexibility here: You can call up the power pins via the "invoke" command. The CAD symbol is usually drawn so it slides over the A-device (or another if you wish) and fits as if it was part of the symbol. You can also place it near the group in the schematic, or down at the bottom for simpler architectures. That's how it ought to be, gives the designer all the freedom.

That's a special case and I'd agree a more "local" power distribution would help. OTOH, in our designs the regulators are "globally" (on the board) controlled.

In our case there is always a PIC in the middle. I don't know how to show the power control code on the schematic. ;-)

That sounds like it solves all the problems.

Ok, then 80% of my designs are special cases :-)

So far I never had a PIC in the middle ...

Sure does. That CAD program is very close to perfect. With one major deficiency and that makes it IMHO useless for any larger design: No hierarchical sheet structure :-(

I don't think anyone here would argue that. ;-)

When I first wrote "PIC" I was kidding; the answer to every question is "PIC". The fact is that we do have a PIC in the middle, on top of a DSP.

Monday we had the design review for the widget I'm working on. My boss really liked the hierarchical (turtles all the way down) organization. I'm not so sure about the other hardware engineer though. ;-) I'm still not to where I can easily determine where to add a hierarchical block or another sheet though. More than one block for a component (FPGA) just seems wrong.

Dead-bugged on top of it with liquid nails glue ...? :-)

Yes, I would never, ever, split a component across several sheets or even just blocks. That makes a royal mess out of a schematic.

Thing I'm doing now, the PLX PCIe chip is three "gate sections" (pcie, backside bus, power) across two sheets. The FPGA is 8 sections (one for each bank, 450 pins or so total) across three sheets. This one board is a 22 sheet schematic... B size sheets.

You never split gate or opamp sections between sheets?

I never do hierarchical schematics. Everything's flat.

John

I _always_ do hierarchical schematics! Each block is a functional cell, making it easier for my layout guy to sort out signal and power routing. And for me to simulate pieces before combining into the total chip.

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

Nope. Only exception is simple logic gates but even then you'd almost have to twist my arm.

Then we have almost opposite CAD habits. But at least we have similar beer taste, only the good stuff :-)

T'is how it ought to be. Just MHO.

It's not surprising that JL would like flat schematics. He does his programming that way. I went to hierarchical programming *long* before I seriously contemplated doing it for schematics.

Yes, and I think it'll reduce our errors significantly. However, I've just run into another OrCad gotcha. Named signals get ruined when buried in a hierarchy. The first instance keeps its name, everything else has its net number appended. It's impossible (without investigating each net) to tell which signal goes with which block.

I hung up on OrCad many years ago. Too many crashes for my taste. Although to be fair, I am known to be brutal on computers. But Eagle doesn't crash. IMHO the last good OrCad was the DOS version, that was absolutely perfect. I never found a bug in it.

Yes, OrCad crashes constantly but they've "fixed" it by doing a save during the crash - sorta. I'm not convinced (less so every day) that it saves everything. Ive noticed that things are disappearing from the schematics. :-(

In PSpice Schematics "appending" a page number is an option. But you're probably using Crapture :-(

HB34:N_6 ???

...Jim Thompson

Sounds more like you were using s***ty computers. On a decent box, I have seen entire seasons pass without such things happening.

Yep, that it is.

Signal Signal_546273 Signal_893273

The number appears to be the numeric part (it's usually of the form N_78234) default net name, if I hadn't assigned a name. In fact, it appears that Crapture only lets you think there is a hierarchy, when it's really just a flat netlist. To define diff-pairs, for example, one has to do it at the flat level. No can do in the hierarchy or schemaitc level. It really is crap.

Can't you ever get anything right, AlwaysWrong?

What happens to reference designators in a hierarchical schematic?

John

Nothing. Blocks become subcircuits... block HB1 netlists as X_HB1.

...Jim Thompson